Proximity effect (electron beam lithography)

About: Proximity effect (electron beam lithography) is a research topic. Over the lifetime, 940 publications have been published within this topic receiving 8508 citations.

OPC aware mask and wafer metrology

Abstract: Lithography at its limit of resolution is a highly non- linear pattern transfer process. Typically the shapes of printed features deviate considerably from their corresponding features in the layout. This deviation is known as Optical Proximity Effect, and its correction Optical Proximity effect Correction or OPC. Although many other so-called optical enhancement technologies are applied to cope with the issues of lithography at its limit of resolution, almost none of these can re-store the linearity of the pattern transfer. Hence fully functional OPC has become a very basic requirement for current and future lithography processes. In general, proximity effects are two-dimensional (2d) effects. Thus any measurement of proximity effects or any characterization of the effectiveness of OPC has to be two- dimensional. As OPC modifies shapes in the data for mask writing in a way to compensate for the expected proximity effects of the following processing steps, parameters describing the particular OPC-mask quality is a major concern. One-dimensional mask specifications, such as linewidth mean-to-target and uniformity, pattern placement, and maximum size of a tolerable defect, are not sufficient anymore to completely describe the functionality of a given mask for OPC. Two-dimensional mask specifications need to be evaluated. We present in this paper a basic concept for 2d metrology. Examples for 2d measurements to assess the effectiveness of OPC are given by the application of an SEM Image Analysis tool to an advanced 130nm process.

Electron-beam fabrication of submicron gates for GaAs FET's

Abstract: High‐performance GaAs FET’s with nominal gate lengths of 0.5, 0.75, and 1.0 μm have been fabricated with electron‐beam‐lithography techniques. A hybrid process was developed which only required e‐beam definition of the critical gate level and was otherwise compatible with the fabrication process developed for conventional optically defined gates. The source–drain metallization mask was modified to include alignment marks for the gate level and the source–drain metallization was augmented to give marks after alloying with acceptable secondary electron contrast against the GaAs background: ±2000 A registration was routinely achieved over the 80×80 mil2 field. A test pattern which could be examined optically with rapid turnaround to determine the proper exposures for the various gate lengths was employed. The pattern evaluation was confirmed by resist exposure studies in conjunction with SEM examination. Evaluation of the test pattern together with corrections for the GaAs substrate backscatter and proximity effect allowed control of the gate lengths to ±10% over the entire slice. The gates were tapered at the mesa edge to prevent constriction of the resist over the step. The resist used was polymethyl methacrylate (PMMA) with a nominal thickness of 7500 A and the developed pattern served as the lift‐off mask for 4000–5000 A of aluminum gate metallization. The nominal slice size used for these runs was slightly greater than 1 cm2 (420×420 mil2) and up to 588 devices were patterned in a single pumpdown. The exposure time required per slice, including stage step and alignment, was six minutes. Both small signal and power GaAs FET’s have been fabricated with e‐beam defined gates. Small signal devices with 0.75μm gate lengths had 2.0 dB minimum noise figures with 10 dB gain at 9 GHz. Power devices with 4800‐μm total gate width and 1‐μm gate length had up to 4.1 W output power at 8 GHz with 4 dB gain.

Methods for determining a pattern on a microlithography reticle to minimize proximity effects in pattern elements in chips located on substrate periphery

Abstract: Methods are disclosed for determining a reticle pattern to be defined on a reticle used for charged-particle-beam microlithography performed using a high beam-acceleration voltage. The pattern is determined so as to define pattern elements, destined for transfer-exposure to respective edges of chips, on the reticle in a manner serving to reduce proximity effects in such elements when imprinted on the substrate, whether or not the elements are in peripherally situated chips (located at or near a wafer perimeter) or in chips located centrally on the substrate. On the reticle the profile of such an element is reconfigured as required to reduce proximity effects caused by proximal pattern elements in neighboring chips. To reduce variations in the imprinted profile of such an element in peripherally located chips versus centrally located chips on the substrate, portions of neighboring chips that straddle the substrate edge are imprinted nevertheless. This ensures that the edges of each entire chip imprinted on the substrate experiences the same proximity effect that is offset by the pattern defined by the reticle, regardless of whether the imprinted entire chips are located peripherally or centrally on the substrate.

Charged-particle-beam microlithography methods and reticles for same exhibiting reduced space-charge and proximity effects

Abstract: Methods and reticles are provided for performing charged-particle-beam microlithography in which degradations in transfer accuracy arising from the space-charge effect and/or resist heating are reduced A reticle is divided into multiple exposure units (eg, subfields) each having at least one pattern feature, and each exposure unit is divided into multiple subunits Certain features include non-exposed regions having dimensions larger than the resolution limit of the projection-optical system used to project the reticle pattern onto the substrate Also, the non-exposed regions are desirably smaller than the dimensional limit at which resolution is impossible due to the proximity effect With stencil reticles, the non-exposed regions are preferably provided at boundaries between complimentary pairs of large-dimension features inside exposure units having different feature densities The non-exposed regions absorb backscattered electrons from the exposure doses received by surrounding portions of the feature The dose represented by the backscattered electrons is typically above a threshold value for developing the resist Such features reduce the feature-density variation of the pattern as defined on the reticle

Mask for Forming Minute Pattern

Abstract: PURPOSE: A mask for forming a fine pattern is provided to be capable of maximizing the resolution of semi-dense patterns by restraining the optical proximity effect using a scattering bar assist pattern. CONSTITUTION: A mask for forming a fine pattern comprises a quartz substrate(21), a light shielding layer(22) formed on the quartz substrate, and a scattering bar assist pattern(23) formed on the light shielding layer. The scattering bar assist pattern(23) is located corresponding to both sides of isolated pattern or semi-dense pattern of the light shielding layer(22). At this time, the light shielding layer(22) has a half-ton PSM(Phase Shift Mask) type.