scispace - formally typeset
Search or ask a question

Showing papers on "Pulse-frequency modulation published in 2007"


Journal ArticleDOI
TL;DR: A novel modulation strategy for a neutral-point-clamped converter that can completely remove the low-frequency voltage oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads is presented.
Abstract: This paper presents a novel modulation strategy for a neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based pulsewidth modulation. Nevertheless, it can generate the maximum output-voltage amplitudes that are attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm and, hence, can be processed very quickly. The only drawback of this strategy is that the switching frequencies of the devices are one third higher than those of standard sinusoidal pulsewidth modulation. A control loop for balancing the voltages on the dc-link capacitors is also proposed. This balancing strategy is designed, so that it does not further increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment.

260 citations


Journal ArticleDOI
11 Jul 2007
TL;DR: In this article, a dual-mode dc to dc step-down switching regulator/converter with high conversion efficiency has been proposed for single-cell lithium-ion battery supply applications.
Abstract: This paper presents the design of a novel wide output current range dual-mode dc to dc step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Under light load condition the converter enters PFM mode. The function of closing internal idle circuits is implemented to save unnecessary switching losses. The converter can be switched to PWM mode when the load current is greater than 100 mA. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 mum polycide CMOS process. The range of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95% at 50 mA load current. Above 85 % conversion efficiency can be reached for load current from 3 to 460 mA.

217 citations


Journal ArticleDOI
TL;DR: The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance.
Abstract: Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance

208 citations


Proceedings ArticleDOI
05 Mar 2007
TL;DR: In this article, the authors present the design of a RF pulse width modulator (RF-PWM) for switched-mode power amplification of varying envelope signals using squarewave signals with varying width and subsequently drive a class D-type power amplifier.
Abstract: This paper presents the design of a RF pulse width modulator (RF-PWM) for switched-mode power amplification of varying envelope signals. The general idea is to modulate the varying envelope signal using squarewave signals with varying width and subsequently drive a class D-type power amplifier. The linearity in the modulator is ensured by a novel combination of low frequency feedback combined with predistortion. Measurements on a frequency wise down-scaled prototype show that the RF-PWM modulator modulates a UMTS signal with more than 17 dB margin to the modulation mask and EVM below 0.5% RMS. This leads to the conclusion that sufficient linearity and modulation accuracy can be obtained using RF pulse width modulation

52 citations


Journal ArticleDOI
TL;DR: In this paper, the power and bandwidth efficiencies, power spectrum distribution, and the ability to resist intersymbol interference of PPM and L-PWM were compared, and it was shown that PPM has advantages in power efficiency and an approximately uniform spectral distribution.
Abstract: Different modulation methods for optical wireless have different power and bandwidth efficiencies. Each approach has a direct bearing on the quality and effectiveness of wireless optical communications. As two prime examples, pulse position modulation (PPM) and pulse width modulation (PWM) are compared. The comparison includes the power and bandwidth efficiencies, the power spectrum distribution, and the ability to resist intersymbol interference. Compact system models of multilevel digital PPM (L-PPM), and multilevel digital PWM (L-PWM) are also introduced. The results show that L-PPM has advantages in power efficiency and an approximately uniform spectral distribution, whereas L-PWM has a greater ability to resist intersymbol interference.

35 citations


Proceedings ArticleDOI
04 Dec 2007
TL;DR: This paper shows that it is suitable to use a triangle-wave comparison PWM which has coherent spectrum peaks of spurious due to switching and the minimum switching/sampling rate is required as five times high as the baseband bandwidth that is much less than that for the delta-sigma modulation.
Abstract: High efficiency transmitter architecture based on Kahn envelope elimination and restoration using PWM envelope modulation schemes is studied. At the final stage, it modulates a constant envelope radio frequency signal by on-off keying or "burst width modulation" directly with the PWM or delta-sigma modulated envelope signal without a lowpass filter. This paper shows that it is suitable to use a triangle-wave comparison PWM which has coherent spectrum peaks of spurious due to switching. It is derived from theoretical analysis that the minimum switching/sampling rate is required as five times high as the baseband bandwidth that is much less than that for the delta-sigma modulation. Simulation results show good modulation quality with the EVM less than 1 percent for raised cosine roll-off filtered 64 QAM.

35 citations


Patent
09 Nov 2007
TL;DR: In this paper, a circuit and a method for reducing output noise when a pulse width modulation mode is started is presented, and the first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit.
Abstract: A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

26 citations


Patent
03 Oct 2007
TL;DR: In this article, a PWM/PFM control circuit has a differential time generating means for forming a differential-time signal representing the difference between the pulse width of PWM and PFM control signals, and the oscillation frequency of a reference signal serving as a reference for forming the PWM control signal is controlled based on the differential time signal.
Abstract: A PWM/PFM control circuit has a differential time generating means for forming a differential time signal representing a differential time corresponding to a difference between the pulse width of a PWM control signal and the pulse width of a PFM control signal on condition that the pulse width of the PWM control signal is smaller than the pulse width of the PFM control signal, and the oscillation frequency of a reference signal serving as a reference for forming the PWM control signal is controlled based on the differential time signal to a low value in accordance with the differential time.

25 citations


Patent
13 Sep 2007
TL;DR: In this article, an analog, duty cycle replicating frequency converter extracts duty cycle information from an input, pulse width modulated signal and generates an output pulse width modulation signal of the same duty cycle at a different frequency without regard to the frequency of the input signal.
Abstract: An analog, duty cycle replicating frequency converter extracts duty cycle information from an input, pulse width modulated signal and generates an output pulse width modulated signal of the same duty cycle at a different frequency without regard to the frequency of the input signal. It uses bipolar transistor based circuitry, adaptable to an application specific integrated circuit, to derive voltages representing the on-time and period durations of the input signal, convert these voltages to currents representing the logarithms thereof, generate a voltage representing the difference between the currents, exponentially convert the voltage to a current representing the duty cycle and control an oscillator to generate an output pulse width modulated signal at a predetermined frequency with the duty cycle of the input signal.

24 citations


Journal ArticleDOI
TL;DR: In this paper, a new control scheme of Class-E inverter for induction heating jar applications with clamped voltage characteristics using pulse frequency modulation (PFM) is introduced, which does not need any auxiliary circuit.
Abstract: A new control scheme of Class-E inverter for induction heating jar applications with clamped voltage characteristics using pulse frequency modulation (PFM) is introduced. To reduce the voltage stress of a switch, the proposed PFM control scheme does not need any auxiliary circuit. It can decrease the voltage stress of a switch through the modulation of switching frequency. The Class-E inverter using the proposed control scheme has the advantages of not only the same output power when it is compared with an active clamped class-E (ACCE) inverter, but also zero-voltage-switching, which are characteristics of conventional Class-E and ACCE inverter. The control principles of the proposed method are explained in detail and its validity is verified through experimental results.

23 citations


Proceedings ArticleDOI
01 Nov 2007
TL;DR: In this paper, a simple PWM technique of capacitor voltage balance for three-level inverters is presented, where only DC-link voltage sensor is required and the number of sectors per sextant is divided into six sectors rather than four.
Abstract: This paper presents a simple PWM technique of capacitor voltage balance for three-level inverters. For the presented PWM technique only DC-link voltage sensor is required. As compared to previous methods, current sensor is not required for the presented technique. Moreover, number of sectors per sextant is divided into six sectors rather than four. The presented PWM technique slightly modifies conventional space vector modulation technique by adding a control factor which is used to adjust the distribution of vector times of middle voltage vector according to the voltage of DC-link capacitors. The presented PWM technique is realized using a digital signal processor and experimental results show that the voltage balance of the DC-link capacitors can be achieved even the voltage difference is up to 100 V for a 300 V DC-link system. The harmonic contents of the presented PWM technique and the effect of control factor on the voltage balance are also investigated in this paper. Experimental results derived from a three-phase induction motor drive system are presented to confirm the presented techniques.

Patent
06 Jun 2007
TL;DR: In this paper, a multi-frequency wireless communication system is described, which includes an input modulation unit, a phase modulation system, and an amplitude modulation system coupled to the input unit and providing amplitude modulation on the output signal.
Abstract: A transmitter circuit is disclosed for use in a multi-frequency wireless communication system. The transmitter circuit includes an input modulation unit, a phase modulation system, and an amplitude modulation system. The input modulation unit receives at least one signal that is representative of information to be modulated. The phase modulation system is coupled to the input modulation unit and provides a phase modulation on an output signal. The phase modulation system includes a phase detection system and an adjustable power amplifier. The amplitude modulation system is coupled to the input modulation unit and provides amplitude modulation on the output signal. The amplitude modulation system includes an amplitude detection system for providing an output signal to the adjustable power amplifier, and a variable gain amplifier coupled to the adjustable power amplifier.

Journal ArticleDOI
TL;DR: A neural network based online analog modulation recognition of communication signals is presented andoretical simulations and experimental results indicate good performance even at signal-to-noise ratios as low as 5dB.
Abstract: In this paper, a neural network based online analog modulation recognition of communication signals is presented. The proposed system can discriminate between amplitude modulation (AM), frequency modulation (FM), double sideband (DSB), upper sideband (USB), lower sideband (LSB) and continuous wave (CW) modulations. A matlab graphical user interface (GUI) is designed to see the intercepted signal, its power spectral density, frequency and modulation type on the screen of the personnel computer. To achieve correct classification, extensive simulations have been done for training the neural network. Theoretical simulations and experimental results indicate good performance even at signal-to-noise ratios as low as 5dB.

Proceedings ArticleDOI
17 Jun 2007
TL;DR: In this paper, the authors extended the nearest-three virtual-space-vector (NTV2) PWM to the four-level DC-AC converter and proposed a new virtual vector to guarantee the dc-link capacitor voltage balance for any operating condition and load.
Abstract: Several pulsewidth modulation strategies have been proposed for the three-level three-phase diode-clamped dc-ac converter. Among them, the nearest-three virtual-space-vector (NTV2) pulsewidth modulation (PWM) guarantees the dc-link capacitor voltage balance under any operating condition, provided that the addition of the three phase currents equals zero. This paper extends this modulation concept to the four level converter. The new virtual vectors are presented and practical modulation solutions are defined. Conventional nearest-three space vector (NTV) PWM cannot comprehensively achieve balanced and stable dc-link voltages. The proposed modulation solutions enable the practical use of the four-level converter since they guarantee the dc-link capacitor voltage balance for any operating condition and load, provided that the addition of three- phase currents equals zero. Simulation and experimental results prove the goodness of the presented approach.

Proceedings ArticleDOI
01 Sep 2007
TL;DR: In this article, the influence of different types of carriers on the converter performances in frame of a general algorithm was investigated and some novel strategies and compared with the already known methods, which can be found in Table 1.
Abstract: A multilevel carrier-based pulse width modulation (CB-PWM) strategy has M-l carriers which can be differently selected from several aspects. The specifications and allocation of carriers strongly affect the converter performances. While investigating the influence of different types of carriers on the converter performances in frame of a general algorithm, the paper introduces some novel strategies and compares them with the already known methods.

Patent
28 Aug 2007
TL;DR: In this paper, the authors present a method of controlling a power converter that can be used to interface to a power grid or supply network operating at a frequency that is nominally fixed (say at 50 Hz), but which can be varied as a way of controlling power imbalanced within the network as a whole.
Abstract: The present invention provides a method of controlling a power converter that can be used to interface to a power grid or supply network operating at a frequency (Fnet) that is nominally fixed (say at 50 Hz, for example) but which can be varied as a way of controlling power imbalanced within the network as a whole. The power converter can include a network bridge that operates in accordance with the pulse width modulation (PWM) strategy having a switching frequency (Fpwm), a nominal switching frequency (Fpwm_nom) and a number of pulses per period (Pulse_Number). The method comprising the step of varying the switching frequency (Fpwm) of the PWM strategy in accordance with the time-varying frequency (Fnet) of the supply network to achieve only integer odd harmonics of the time-varying frequency (Fnet) and adjusting the number of pulses per period (Pulse Number) in accordance with the time-varying frequency (Fnet) of the supply network to maintain a switching frequency (Fpwm) that is less than, or equal to, the nominal switching frequency (Fpwm_nom).

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the effect of average and quasi-peak (QP) detectors on the reduction of the differential-mode conducted electromagnetic interference (EMI) of the offline boost power-factor correction converter.
Abstract: This paper investigates the use of switching frequency modulation in the reduction of the differential-mode conducted electromagnetic interference (EMI) of the offline boost power-factor correction converter. In particular, the EMI benefits obtained with modulation frequencies at and in excess of twice the line frequency are considered, incorporating the influence of average and quasi-peak (QP) detectors into the analysis and measurements. It is concluded that there is no significant change in the QP measurement unless the modulation frequency exceeds half the resolution bandwidth; however, up to 8-dB reduction in the average measurement, with no change in the QP measurement, can be obtained with modulation at twice the line frequency, for a switching frequency deviation of 20%. A digital modulation algorithm was devised and implemented using a digital-signal-processor-controlled converter. The reduction in the average detector measurement obtained for the digital modulation was comparable to that predicted for the linear modulation, but it delivers a more well-defined and predictable conducted EMI spectrum.

Patent
Lin Hsiao-Chyi1
19 Apr 2007
TL;DR: In this paper, a modified phase modulation technique was proposed to remove the down spread limitation present in traditional PM implementations, and also provided better jitter performance and lower cost than traditional PM implementation.
Abstract: Spread spectrum clock generation (SSCG) using phase modulation. A first clock signal having a first frequency spectrum may be modulated using phase modulation to produce a second clock signal. The phase modulation may include providing a phase modulation profile corresponding to the integrated frequency modulation profile, to adjust a scaling factor used in obtaining the second clock signal. The phase modulation profile may be provided in the form of a pulse or pulses, which may be injected through pulse density modulation or pulse width modulation at the output of a phase frequency detector comprised in a phase locked loop circuit used in generating the second clock signal. This modified phase modulation technique removes the down spread limitation present in traditional PM implementations, and also provides better jitter performance and lower cost than traditional PM implementations.

Patent
27 Sep 2007
TL;DR: In this paper, a voltage converting unit receives an input voltage and outputs an output voltage according to the magnitude of the input voltage by switching operation based on a control clock signal, and a comparing circuit generates a power good pulse signal by comparing the output voltage with a reference voltage.
Abstract: A converter circuit is provided herein. In the converter, a voltage converting unit receives an input voltage and outputs an output voltage according to the magnitude of the input voltage by switching operation based on a control clock signal. A comparing circuit generates a power good pulse signal by comparing the output voltage with a reference voltage. A pulse width frequency modulation circuit receives the power good pulse signal and a source clock signal to provide the control clock signal. The pulse width of the source clock signal is varied gradually and the frequency of the source clock signal is also changed during a period that the power good pulse signal remains in the first logic state, and the pulse width frequency modulated source clock signal is output as the control clock signal.

Proceedings ArticleDOI
24 Apr 2007
TL;DR: Three representations are proposed to model variable heart timing in the case of normal sinus rhythm (pulse process with time jitter, random inter-pulse interval and integral pulse frequency modulation model).
Abstract: Spectral analysis belongs to widely used method for biomedical data exploration. In order to interpret spectrum correctly, prior knowledge how various phenomena affect the spectrum of analyzed signal is desirable. Spectrum of ECG signal is affected by waveform component shapes, their time positions within cardiac cycle as well as by regularity of heart period. This paper deals with effect of heart rate variability on ECG signal spectrum. Three representations are proposed to model variable heart timing in the case of normal sinus rhythm (pulse process with time jitter, random inter-pulse interval and integral pulse frequency modulation model). Properties of corresponding spectra are theoretically studied and compared with real-world signals from PhysioBank data archive.

Patent
Russell John Fagg1
28 Aug 2007
TL;DR: In this paper, an apparatus for wireless communications including a signal generator adapted to generate a substantially periodic signal including a plurality of cycles, and a modulator adapted to modulate an amplitude, a phase or both the amplitude and the phase of the periodic signal on a per cycle basis.
Abstract: An apparatus for wireless communications is disclosed including a signal generator adapted to generate a substantially periodic signal including a plurality of cycles, and a modulator adapted to modulate an amplitude, a phase or both the amplitude and the phase of the periodic signal on a per cycle basis. In one aspect, the modulator is adapted to modulate the amplitude, the phase, or both the amplitude and phase of the periodic signal with a defined modulation signal. In another aspect, the defined modulation signal includes a substantially root raised cosine signal. In yet another aspect, the defined modulation signal is configured to achieve a defined frequency spectrum for the modulated periodic signal.

Patent
04 Dec 2007
TL;DR: In this article, a duty cycle detecting circuit for pulse width modulation (PWM) was proposed, which consists of a clock generating circuit, a sampling circuit, and a calculation circuit.
Abstract: A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal.

Patent
16 Jan 2007
TL;DR: In this article, a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band is provided, provided that the PLL unit (100) is equipped with a phase comparator.
Abstract: Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation signal input means for inputting a first modulation signal to a divider (112) or a phase comparator (113) of the PLL unit (110); second modulation signal input means for DA converting the digital modulation signal in a DA converter (116) to generate an analog second modulation signal and inputting it to a voltage control oscillator (111) of the PLL unit (110); a second divider for dividing the output signal of the voltage control oscillator (111); and control means for generating a center frequency control signal, a gain control signal, and a second division ration control signal according to the channel selection signal and the control voltage inputted to the voltage control oscillator (111) and supplying them to the divider (112), the DA converter (116), and the second divider (114), respectively.

Proceedings ArticleDOI
01 Nov 2007
TL;DR: In this article, a simplified carrier-based control of matrix converter is modified to operate the converter in the over-modal region, and the maximum output to input voltage transfer ratio with 6-step square wave output voltage is found to be 0.95 which is higher than the 0.866 intrinsic limit of the matrix converter.
Abstract: In this paper, the simplified carrier-based control of matrix converter is modified to operate the converter in the over- modulation region. Both the input-side and output-side over- modulation modes have been studied and their limits of operation are derived. With output-side over-modulation, the maximum output to input voltage transfer-ratio with 6-step square wave output voltage is found to be 0.95 which is higher than the 0.866 intrinsic limit of the matrix converter. With input-side over- modulation the maximum voltage transfer-ratio is found to be 0.908 while still being able to control the power factor of the input currents. With simultaneous input and output-side over- modulation, a unity voltage transfer-ratio is achieved. This improvement in the voltage transfer-ratio in the above three cases is achieved at the cost of low frequency distortion in the output voltages and input currents. With simultaneous input and output- side over-modulation, a voltage transfer-ratio of 0.958 is achieved without significantly increasing the harmonics in the input currents and output voltages. Theoretical calculations are supported by experimental results on a laboratory prototype.

Patent
Jae-Wook Lee1
26 Jan 2007
TL;DR: In this article, the PWM signal includes a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data.
Abstract: For PWM (pulse width modulation), a counter generates a count signal by counting a clock signal 2 n times for one period of the count signal. A PWM circuit generates a PWM signal from an n-bit pulse code modulation (PCM) data. The PWM signal includes a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data. A same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding the most and least significant bits of the n-bit PCM data.

Patent
09 Nov 2007
TL;DR: In this paper, a DC-DC converter reduces reverse current and maintains high conversion efficiency under a light load by using a reverse flow detection circuit and a detection signal invalidation circuit.
Abstract: A DC-DC converter reducing reverse current and maintaining high conversion efficiency under a light load. The DC-DC converter perform pulse width modulation (PWM) or pulse frequency modulation (PFM) and includes a drive control circuit generating a first drive signal and a second drive signal activating and inactivating a first transistor and a second transistor in a complementary manner. A reversed flow detection circuit detects current flowing to the second transistor and generates a detection signal controlling activation and inactivation of the second transistor. A detection signal invalidation circuit, coupled to the reversed flow detection circuit and the drive control circuit, receiving an operation switch signal and invalidating the detection signal in response to the operation switch signal during at least a certain period of the PWM.

Patent
12 Sep 2007
TL;DR: In this article, the modulation current of a laser included as a component of an optical transceiver module, such as an Optic Transceiver Module (OTM), is discussed.
Abstract: Systems and methods for controlling the modulation current of a laser included as a component of an optical transmitter, such as an optical transceiver module, are disclosed. Control of the modulation current, which affects various laser operational parameters, including extinction ratio and optical modulation amplitude, enables operation of the laser to be optimized, thereby enabling reliable transceiver performance to be achieved. In one embodiment, a method for modifying the modulation current in an optical transceiver module includes first sensing analog voltage data that proportionally relates to an actual modulation current of the laser. Once sensed, the analog voltage data are converted to digital voltage data. Using the digital voltage data, the actual modulation current of the laser is determined, then a desired modulation current is determined. Should a discrepancy exist between the actual and desired modulation currents, the actual modulation current is modified to match the desired current.

Patent
29 Mar 2007
TL;DR: In this article, the authors propose a modulation switching scheme to switch a modulation format without requiring a plurality of modulators corresponding to respective modulation formats, and demonstrate that the modulation scheme can be applied to optical modulation devices.
Abstract: PROBLEM TO BE SOLVED: To flexibly switch a modulation format without requiring a plurality of modulators corresponding to respective modulation formats. SOLUTION: The optical modulation device 100 can switch a modulation format according to a modulation switching information. A Mach-Zehnder type modulator 120 modulates carrier light on the basis of a drive signal. An oscillator 140 superimposes a signal of a prescribed frequency on the drive signal. A bias supply part 162 supplies bias voltage corresponding to a component of the prescribed frequency included in signal light modulated by the Mach-Zehnder type modulator 120 to the Mach-Zehnder type modulator 120. A switch 170 switches: a first route 171 for superimposing the signal of the prescribed frequency to the drive signal; and a second route 172 for superimposing the signal of the prescribed frequency to the bias voltage. A modulation switching part 180 controls the drive signal and the switch 170 according to the modulation switching information. COPYRIGHT: (C)2009,JPO&INPIT

Patent
17 May 2007
TL;DR: A power supply topology with pulse width modulation frequency control allows the use of an inductor with higher inductance in a converter as discussed by the authors, which can achieve high efficiency during a light load condition and also suitable for a heavy load condition.
Abstract: A power supply topology with pulse width modulation frequency control allows the use of an inductor with higher inductance in a converter. By controlling the switching frequency of the pulse width modulation signal, the inductor can achieve high efficiency during a light load condition and is also suitable for a heavy load condition.

Proceedings ArticleDOI
01 Oct 2007
TL;DR: Simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes, with suitable control and mode switch method.
Abstract: A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed This converter works in PWM mode on heavy load condition In order to improve efficiency, it switches to PFM mode on light load condition With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 926% Simulated and implemented in CSMC 05 mum CMOS process