Topic
QR decomposition
About: QR decomposition is a research topic. Over the lifetime, 3504 publications have been published within this topic receiving 100599 citations. The topic is also known as: QR factorization.
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TL;DR: A new algorithm for computing theQR factorization of anm×n Toeplitz matrix inO(mn) operations is presented, exploiting the procedure for the rank-1 modification and the fact that both principal (m−1)×(n −1) submatrices of the Toe Plitz matrix are identical.
Abstract: This paper presents a new algorithm for computing theQR factorization of anm×n Toeplitz matrix inO(mn) operations. The algorithm exploits the procedure for the rank-1 modification and the fact that both principal (m−1)×(n−1) submatrices of the Toeplitz matrix are identical. An efficient parallel implementation of the algorithm is possible.
80 citations
TL;DR: Lower bounds and upper bounds on |G|/|L| in terms of |E|/ |A| are given and perturbation bounds are given for the QR factorization of a complexm ×n matrixA of rankn.
Abstract: LetA, A+E be Hermitian positive definite matrices. Suppose thatA=LL
H andA+E=(L+G)(L+G)H are the Cholesky factorizations ofA andA+E, respectively. In this paper lower bounds and upper bounds on |G|/|L| in terms of |E|/|A| are given. Moreover, perturbation bounds are given for the QR factorization of a complexm ×n matrixA of rankn.
79 citations
21 May 2006
TL;DR: In this paper, the authors proposed a triangular systolic array for large size complex matrices using a three angle complex rotation approach that provides significant reduction of latency (systolic operation time) and makes the upper triangular matrix R has only real diagonal elements.
Abstract: The novel CORDIC-based architecture of the triangular systolic array for QRD of large size complex matrices is presented. The proposed architecture relies on QRD using a three angle complex rotation approach that provides significant reduction of latency (systolic operation time) and makes the QRD in such a way that the upper triangular matrix R has only real diagonal elements.
79 citations
27 May 2007
TL;DR: A new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area and can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.
Abstract: Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily efficient. In this paper, a new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area. Furthermore, the hardware can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.
78 citations
23 May 2005
TL;DR: This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices using arithmetic operations with 12 bit fixed-point representation and shows that traditional triangular array architectures employing O(n/sup 2/) communicating processors can be mapped onto a scalable linear array architecture with only O( n) processors.
Abstract: This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R/sup -1/ with Q. We show that traditional triangular array architectures employing O(n/sup 2/) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system.
78 citations