Quadrature mirror filter

About: Quadrature mirror filter is a research topic. Over the lifetime, 955 publications have been published within this topic receiving 28900 citations.

QMF banks design and implementation perspectives

Abstract: A framework for the design of two-channel quadrature mirror filter (QMF) banks is described. The design is performed using FIR (finite impulse response) as well as IIR (infinite impulse response) filters. A comparison is provided among design techniques to illustrate the advantages and disadvantages of such filters, and their implementation is considered. >

A property of digital quadrature filters

Abstract: A relationship is derived for digital linear-phase quadrature filters of even length. It is shown that their impulse responses are simply related through an alternate sign inversion operation.

Mirror suppression circuit in a quadrature demodulator

Abstract: Mirror suppression circuit and receiver using such mirror suppression circuit comprising a first quadrature signal path coupled between quadrature signal input and output terminals and including an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal comprising a pair of in-phase and phase quadrature signal components. To obtain a suppression of both amplitude and phase imbalance of said carrier modulated quadrature signal as well as signal amplitude variations, a quadrature output of said error correction circuit being coupled through a first filter circuit for a selection of said quadrature signal to a first quadrature input of an error detection circuit, said first quadrature signal path being coupled prior to said first filter circuit through a second quadrature signal path to a second quadrature input of said error detection circuit, said error detection circuit detecting amplitude and phase errors and providing amplitude and phase control signals to amplitude and phase control inputs of said error correction circuit for a negative feed back of said amplitude and phase errors to said error correction circuit, said amplitude control signal varying with at least one of products Iw*Iref and Qw*Qref and said phase control signal varying with at least one of products Iw*Qref and Qw*Iref, Iw and Qw, respectively Iref and Qref, representing the in-phase and phase quadrature signal components of said quadrature signal at the first quadrature input of the error detection circuit, respectively the in-phase and phase quadrature signal components of a quadrature reference signal occurring at the negative carrier frequency of said quadrature signal at the second quadrature input of the error detection circuit.

ELINT Signal Processing on Reconfigurable Computers for Detection and Classification of LPI Emitters

Abstract: : This thesis describes the implementation of an ELINT algorithm for the detection and classification of Low Probability of Intercept (LPI) signals. The algorithm was coded in the C programming language and executed on a Field Programmable Gate Array based reconfigurable computer; the SRC-6 manufactured by SRC Computers, Inc. Specifically, this thesis focuses on the preprocessing stage of an LPI signal processing algorithm. This stage receives a detected signal that has been run through a Quadrature Mirror Filter Bank and outputs the preprocessed signal for classification by a neural network. A major value of this study comes from comparing the performance of the reconfigurable computer to that of supercomputers and embedded systems that are currently used to solve the signal processing needs of the United States Navy.

Multiplier-less implementation of quadrature mirror filter

Abstract: The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an efficient way of implementing the lattice wave digital filter (LWDF) structure of the quadrature mirror filter (QMF) with canonic signed digit (CSD) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow carry propagation adders. This increases the speed of the overall filter structure compared to the conventional way of implementing the filter with CSD coefficients. The proposed QMF is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.