Topic
Quadrature mirror filter
About: Quadrature mirror filter is a research topic. Over the lifetime, 955 publications have been published within this topic receiving 28900 citations.
Papers published on a yearly basis
Papers
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01 Jan 2017TL;DR: Analog baseband circuits, including filters and programmable gain amplifiers (PGA), are indispensable in wireless sensors and communication systems and demand low-noise and linear baseband channel select filters to accommodate the large dynamic range of the input signals.
Abstract: Analog baseband circuits, including filters and programmable gain amplifiers (PGA), are indispensable in wireless sensors and communication systems. Portable devices continue to drive the need for circuits that achieve low power without sacrificing linearity. These analog baseband filters typically consume tens of mW and have a considerable impact on the total power consumption of a transceiver. Wireless receivers today demand low-noise and linear baseband channel select filters to accommodate the large dynamic range of the input signals. Power dissipation and die area of these filters must also be as small as possible. Analog frond ends are usually integrated with digital function blocks in recent mixed-signal Soc applications including data communication and image processing systems. Low power and small area ADCs with 8–10b accuracy operating several tens of MS/s are considered important building blocks. However each ADC has to he preceded by a front end anti-alias filter with cut off frequency in MHz range. There are two major concerns when we design a wideband LPF. One is the selection of filter LCR prototype, that is, Butterworth, Chebychev, Bessel etc. The other is the selection between G m -C and active-RC.
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01 Nov 2015TL;DR: In this paper, Quadrature Mirror Filter (QMF) is used as a base filter bank for sub band applications and sub band coding in signal processing in the signal processing.
Abstract: Filter banks are used like as sub band applications and sub band coding in the signal processing. Quadrature Mirror Filter (QMF) is a base filter bank for these applications. In this work, QMF bank designed for specific signal. QMF prototype filter parameters are designed with Differential Evolution Algorithm.
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30 Dec 2022TL;DR: In this paper , an improved Differential Evolution based Sine Cosine Algorithm (DESCA) is proposed to design a near-perfect reconstruction (NPR) Quadrature Mirror Filter (QMF) bank.
Abstract: This paper proposes an improved Differential Evolution based Sine Cosine Algorithm (DESCA), to design a Near-Perfect Reconstruction (NPR) Quadrature Mirror Filter (QMF) bank. The proposed population-based DESCA algorithm is used here to optimize the Finite Impulse Response (FIR) filter coefficients that function as the prototype filter of the QMF filter bank. The proposed DESCA algorithm is compared with latest state-of-the-art algorithms which ensure the effectiveness of the proposed algorithm. Field Programmable Gate Array (FPGA) implementation is done for the proposed DESCA algorithm for different filter taps and simulated with Xilinx ISE Design Suite. The performance result of the proposed DESCA algorithm demonstrates its ability in solving complex multimodal problems with respect to the existing state-of-the-art algorithms.
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TL;DR: The study and implementation of a Quadrature Mirror Filter in VHDL will be aimed to realize the equalizer for wireless communication system.
Abstract: In this paper a Quadrature Mirror Filter is implemented in VHDL, for wireless communication applications. The Quadrature Mirror Filter (QMF) basically is a parallel combination of a High Pass Filter (HPF) and Low Pass Filter (LPF), which performs the action of frequency subdivision by splitting the signal spectrum into two spectra. The QMF implementation is carried out on FPGA platform. The Xilinx IP Core generator will be used for instantiating the standard Xilinx parts. Xilinx ISE will be used to carry out the synthesis and bit file generation. The obtained Synthesis Report for implemented QMF will be used to analyze the occupied area and power dissipation. The study and implementation will be aimed to realize the equalizer for wireless communication system. Modelsim Xilinx Edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis and bit file generation. The Xilinx Chip scope will be used to test the results on Spartan 3E 500K FPGA board.