Showing papers on "Quantum capacitance published in 2002"

Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors

Abstract: A simple model for ballistic nanotransistors, which extends previous work by treating both the charge control and the quantum capacitance limits of MOSFET-like transistors, is presented. We apply this new model to MOSFET-like carbon nanotube FETs (CNTFETs) and to MOSFETs at the scaling limit. The device physics for operation at ballistic and quantum capacitance limits are explored. Based on the analysis of recently reported CNTFETs, we compare CNTFETs to MOSFETs. The potential performance advantages over Si that might be achieved at the scaling limit are established by using the new model.

An RF circuit model for carbon nanotubes

Abstract: We develop an rf circuit model for single walled carbon nanotubes for both dc and capacitively contacted geometries. By modeling the nanotube as a nano-transmission line with distributed kinetic and magnetic inductance as well as distributed quantum and electrostatic capacitance, we calculate the complex, frequency dependent impedance for a variety of measurement geometries. Exciting voltage waves on the nano-transmission line is equivalent to directly exciting the yet-to-be observed one dimensional plasmons, the low energy excitation of a Luttinger liquid.

Atomistic capacitance of a nanotube electromechanical device

Abstract: An atomistic capacitance is derived for a single-wall carbon nanotube in a nano-electromechanical device Multi-scale calculation is performed using a continuum model for the geometrical capacitance, and statistical and quantum mechanical approaches for the quantum capacitance of the nanotube The geometrical part of the capacitance is studied in detail using full three-dimensional electrostatics Results reported in this paper are useful for compact modeling of the electronic and electromechanical nanotube devices

Quantum C-V modeling in depletion and inversion: accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs

Abstract: Presented in this paper is a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate-depletion effect. The model enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs. The main quantum effect consists of the inversion capacitance of two-dimensional (2-D) electrons masking the true gate-oxide thickness, t/sub OX/. The quantum mechanical and gate depletion effects necessitate 6-10 /spl Aring/ equivalent oxide thickness correction, which is important for a t/sub OX/ of 4 nm or less. The classical C-V analysis is compared with the quantum results in the light of the data, highlighting the difference between the models. The model is shown in good agreement with experiments and also with numerically calculated results.

First steps towards a quantum capacitance standard at METAS

Abstract: In the 5th framework program of the European Commission, several Metrology Institutes have teamed up in a project (COUNT) aimed at the realization of a primary standard of capacitance based on single electron resistive pumps. In this paper, we report the first steps towards the realization of such a quantum capacitance standard at METAS. The measurement setup is described and the stability diagram of the electron pump, measured at an electronic temperature of 160 mK, is shown. These preliminary results are promising for the future of the experiment.

Low-T/sub c/ ramp-type Josephson junctions for SQUIDs

Abstract: The Josephson tunnel junction is the basic element of a superconducting quantum interference device (SQUID). Amongst other parameters, the junction capacitance determines the characteristics of a (digital) SQUID. In a conventional dc SQUID, reducing the junction capacitance decreases the flux noise of the sensor, whereas in digital SQUIDs, the operating frequency can be increased when reducing the junction capacitance. For digital SQUIDs, this means that not only the flux noise decreases, but also the flux slew rate increases. Slew rates up to l0(8) @ds can be achieved by reducing the junction size to the sub-pm2 level. Using a ramp-type structure allows sub-pm2 Josephson junctions sizes using standard lithography. In this paper we present the first results on low-T, ramp-type Josephson junctions and dc SQUIDs based on these junctions. The first junctions and SQUIDs showed nonhysteretic behavior at 4.2 K caused by the A1 bottom layer in the design.

AC analysis of thin gate oxide MOS with quantum mechanical corrections

Abstract: MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.

Progress in the implementation of the capacitance standard based on single-electron counting at PTB

Abstract: We report on the progress achieved at PTB in setting up an experiment for the realization of a quantum capacitance standard based on the controlled charging of a capacitor by single electrons. An experiment of this kind was suggested and first performed by NIST. In order to enhance the accuracy of the experiment, we use a new kind of single-electron pump and a capacitor with improved design features. The main components for the experiment are presented and discussed.