Showing papers on "Quantum capacitance published in 2009"
TL;DR: The results strongly indicate that the long-standing puzzle about the interfacial capacitance in carbon-based electrodes has a quantum origin, and suggest that charged impurities also influences the quantum capacitance.
Abstract: Graphene has received widespread attention due to its unique electronic properties. Much of the research conducted so far has focused on electron mobility, which is determined by scattering from charged impurities and other inhomogeneities. However, another important quantity, the quantum capacitance, has been largely overlooked. Here, we report a direct measurement of the quantum capacitance of graphene as a function of gate potential using a three-electrode electrochemical configuration. The quantum capacitance has a non-zero minimum at the Dirac point and a linear increase on both sides of the minimum with relatively small slopes. Our findings -- which are not predicted by theory for ideal graphene -- suggest that charged impurities also influences the quantum capacitance. We also measured the capacitance in aqueous solutions at different ionic concentrations, and our results strongly indicate that the long-standing puzzle about the interfacial capacitance in carbon-based electrodes has a quantum origin.
1,492 citations
TL;DR: In this paper, a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field effect transistors (TFETs) is presented, using semiconducting carbon nanotubes as the model channel material.
Abstract: In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.
355 citations
TL;DR: In this article, the bilayer graphene tunnel field effect transistor (TFET) was proposed for fabrication and circuit integration with present-day technology, and it provided high I on/I off ratio at ultralow supply voltage without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons.
Abstract: In this letter, we propose the bilayer graphene tunnel field-effect transistor (TFET) as a device suitable for fabrication and circuit integration with present-day technology. It provides high I on/I off ratio at ultralow supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons. Our investigation is based on the solution of the coupled Poisson and Schrodinger equations in three dimensions, within the non-equilibrium Green's function formalism on a tight binding Hamiltonian. We show that the small achievable gap of only few hundreds of millielectronvolts is still enough for promising TFET operation, providing a large I on/I off ratio in excess of 103 even for a supply voltage of only 0.1 V. A key to this performance is the low quantum capacitance of bilayer graphene, which permits to obtain an extremely small subthreshold swing S smaller than 20 mV/dec at room temperature.
150 citations
TL;DR: The Bilayer Graphene Tunnel Field Effect Transistor (BG-TFET) as discussed by the authors was proposed for fabrication and circuit integration with present-day technology, and it provides high Ion/Ioff ratio at ultra-low supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons.
Abstract: In this work, we propose the Bilayer Graphene Tunnel Field Effect Transistor (BG-TFET) as a device suitable for fabrication and circuit integration with present-day technology. It provides high Ion/Ioff ratio at ultra-low supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons. Our investigation is based on the solution of the coupled Poisson and Schroedinger equations in three dimensions, within the Non-Equilibrium Green (NEGF) formalism on a Tight Binding Hamiltonian. We show that the small achievable gap of only few hundreds meV is still enough for promising TFET operation, providing a large Ion/Ioff ratio in excess of 10^3 even for a supply voltage of only 0.1 V. Key to this performance is the low quantum capacitance of bilayer graphene, which permits to obtain an extremely small sub-threshold swing S smaller than 20 mV/decade at room temperature.
149 citations
TL;DR: This study revealed that the capacitor effective area (A(eff) responding to the AC bias is much smaller than the geometrical area of the graphene sheet, according to the graphene density of states (DOS).
Abstract: A nanoscale investigation on the capacitive behavior of graphene deposited on a SiO2/n(+) Si substrate (with SiO2 thickness of 300 or 100 nm) was carried out by scanning capacitance spectroscopy (SCS). A bias V(g) composed by an AC signal and a slow DC voltage ramp was applied to the macroscopic n(+) Si backgate of the graphene/SiO(2)/Si capacitor, while a nanoscale contact was obtained on graphene by the atomic force microscope tip. This study revealed that the capacitor effective area (A(eff)) responding to the AC bias is much smaller than the geometrical area of the graphene sheet. This area is related to the length scale on which the externally applied potential decays in graphene, that is, the screening length of the graphene 2DEG. The nonstationary charges (electrons/holes) induced by the AC potential spread within this area around the contact. A(eff) increases linearly with the bias and in a symmetric way for bias inversion. For each bias V(g), the value of A(eff) is related to the minimum area necessary to accommodate the not stationary charges, according to the graphene density of states (DOS) at V(g). Interestingly, by decreasing the SiO(2) thickness from 300 to 100 nm, the slope of the A(eff) versus bias curve strongly increases (by a factor of approximately 50). The local quantum capacitance C(q) in the contacted graphene region was calculated starting from the screening length, and the distribution of the values of C(q) for different tip positions was obtained. Finally the lateral variations of the DOS in graphene was determined.
113 citations
01 Jan 2009
87 citations
TL;DR: In this article, an analytical theory for the gate electrostatics and the classical and quantum capacitance of the graphene nanoribbons GNRs and compare it with the exact selfconsistent numerical calculations based on the tight-binding p-orbital Hamiltonian within the Hartree approximation.
Abstract: We present an analytical theory for the gate electrostatics and the classical and quantum capacitance of the graphene nanoribbons GNRs and compare it with the exact self-consistent numerical calculations based on the tight-binding p-orbital Hamiltonian within the Hartree approximation. We demonstrate that the analytical theory is in a good qualitative and in some aspects quantitative agreement with the exact calculations. There are however some important discrepancies. In order to understand the origin of these discrepancies we investigate the self-consistent electronic structure and charge density distribution in the nanoribbons and relate the above discrepancy to the inability of the simple electrostatic model to capture the classical gate electrostatics of the GNRs. In turn, the failure of the classical electrostatics is traced to the quantum mechanical effects leading to the significant modification of the self-consistent charge distribution in comparison to the noninteracting electron description. The role of electron-electron interaction in the electronic structure and the capacitance of the GNRs is discussed. Our exact numerical calculations show that the density distribution and the potential profile in the GNRs are qualitatively different from those in conventional split-gate quantum wires; at the same time, the electron distribution and the potential profile in the GNRs show qualitatively similar features to those in the cleaved-edge overgrown quantum wires. Finally, we discuss an experimental extraction of the quantum capacitance from experimental data.
71 citations
TL;DR: In this paper, the scaling properties of InAs nanowire MOSFETs in the ballistic limit have been investigated, and it has been shown that the InAs NN with diameters scaled below 15-20 nm can operate close to the quantum capacitance limit, assuming a high-kappa dielectric thickness of 1-1.5 nm.
Abstract: We have investigated the scaling properties of [111] InAs nanowire MOSFETs in the ballistic limit. The nanowire band structure has been calculated with an sp3d5 s* tight-binding model for nanowire diameters between 2 and 25 nm. Both the effective band gap and the effective masses increase with confinement. Using the atomistic dispersion relations, the ballistic currents and corresponding capacitances have been calculated with a semianalytical model. It is shown that the InAs nanowire MOSFET with diameters scaled below 15-20 nm can be expected to operate close to the quantum capacitance limit, assuming a high-kappa dielectric thickness of 1-1.5 nm. We have also investigated the evolution of ft and the gate delay, both showing improvements as the device is scaled. The very small intrinsic gate capacitance in the quantum limit makes the device susceptible to parasitic capacitances.
65 citations
01 Dec 2009
TL;DR: In this paper, a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel was proposed and verified with simulations (Nextnano) and experimental measurements on HEMTs with InAs and InGaAs channels down to 30 nm in gate length.
Abstract: We have built a physical gate capacitance model for III–V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the quantum capacitance significantly lowers the overall gate capacitance. In addition, the channel centroid capacitance is also found to have a significant impact on gate capacitance. Our model provides a number of suggestions for capacitance scaling in future III–V FETs.
36 citations
01 Jan 2009
35 citations
TL;DR: In this article, a comparison of nanowire FETs (NWFETs) of identical geometries but operating in two different regimes, namely, the quantum capacitance and classical capacitance (CC) regimes, is presented.
Abstract: A comparison of nanowire FETs (NWFETs) of identical geometries but operating in two different regimes, namely, the quantum capacitance (QC) and classical capacitance (CC) regimes, is presented n-type InSb and InAs NWFETs up to ~50 nm in diameter operate in the QC limit (QCL), and the corresponding p-type NWFETs operate in the CC limit Drive currents at a fixed gate overdrive for the n- and p-type devices are found to be well matched Nevertheless, the p-type devices have twice the delay times, half the intrinsic cutoff frequencies, twice the power-delay products, and four to five times the energy-delay products of the n-type devices, assuming transport is ballistic Analytical expressions are derived for the QC, the current, the charge, the power-delay product, the energy-delay product, the gate delay time, and the cutoff frequency for a single-moded device operating in the QCL The expressions for the power-delay product, energy-delay product, and the cutoff frequency are fundamental limits for such devices
TL;DR: In this paper, the quantum capacitance of individual semiconducting and small band gap single walled carbon nanotubes (SWNTs) was measured and attributed to strong electron correlation in SWNTs.
Abstract: We report measurements of the quantum capacitance of individual semiconducting and small band gap single walled carbon nanotubes (SWNTs). The observed quantum capacitance, 82 aF/μm for a semiconducting SWNT with chiral index (16,8) and 10.3 aF/μm for a small band gap SWNT upon Fermi level lying at the first subband are remarkably smaller than those originating from the density of states. We attribute the discrepancy to a strong electron correlation in SWNTs and derive the Luttinger parameter g of 0.25–0.3 for the (16,8) SWNT and of 0.32 for a small band gap SWNT.
24 May 2009
TL;DR: Since the interconnect performance determines the IC operations, this proposed monolithic GNR electronics open new opportunities to establish high-performance nanoscale ICs.
Abstract: In this paper, multi-layer graphene nanoribbon (GNR) is proposed as an emerging interconnect solution, which can be integrated with GNR devices to establish a monolithic GNR circuit. Both interconnect resistance and gate capacitance in this circuit are significantly reduced, leading to an RC delay improvement up to 60%. Since the interconnect performance determines the IC operations, this proposed monolithic GNR electronics open new opportunities to establish high-performance nanoscale ICs.
TL;DR: In this paper, a balanced circuit implementation of a nonlinear carbon nanotube (CNT) quantum capacitance circuit is presented and the transconductance conversion gain for the nonlinear CNT quantum capacitor circuit is derived.
Abstract: In this paper, analog circuit applications of a nonlinear carbon nanotube (CNT) quantum capacitance such as frequency doublers and mixers are proposed. We present a balanced circuit implementation and derive the transconductance conversion gain for the nonlinear CNT quantum capacitor circuit. The balanced topology results in robust circuit performance that is insensitive to extrinsic capacitances and parasitic resistances, and is immune to the resistance of metallic nanotubes that may be in the channel. The ballistic quantum capacitance is useful up to several terahertzs (THzs), making it suitable for low-noise THz sources. Additionally, the fundamental bandwidth and performance limitations imposed by the quantum conductance and inductance are discussed.
TL;DR: In this paper, a pair of Cooper-pair boxes coupled with a fixed capacitor using spectroscopy and measurements of the ground-state quantum capacitance is characterized and used to estimate the concurrence or degree of entanglement between the two qubits.
Abstract: We characterize a pair of Cooper-pair boxes coupled with a fixed capacitor using spectroscopy and measurements of the ground-state quantum capacitance. We use the extracted parameters to estimate the concurrence or degree of entanglement between the two qubits. We also present a thorough demonstration of a multiplexed quantum capacitance measurement technique, which is in principle scalable to a large array of superconducting qubits.
TL;DR: In this article, a self-consistent Schrodinger-Poisson solver was used to simulate room temperature capacitance-voltage characteristics of silicon (Si) nanowire gate-all-around MOS structures with radius les 10 nm.
Abstract: We simulate room temperature capacitance-voltage characteristics of silicon (Si) nanowire gate-all-around MOS structures with radius les 10 nm using a self-consistent Schrodinger- Poisson solver in cylindrical coordinates with full treatment of the transverse quantum confinement. In this paper, we compare our simulation results with the latest capacitance measurements on single Si nanowire pMOS and nMOS devices in the subfemtofarad range. We also propose to probe the density-of-states features of the Si channel from the capacitance-voltage characteristics at room temperature measurements using dC/dV dependence and illustrate the idea by employing the latest measurements, our quantum and Medici (Synopsys) simulations, as well as a simplified analytical model.
TL;DR: In this article, the authors proposed and demonstrated wide-band capacitance measurements on a semiconductor double-quantum dot (DQD) to study tunneling dynamics by applying phase-tunable high-frequency signals independently to the DQD and a nearby quantum-point-contact charge detector.
Abstract: We propose and demonstrate wide-band capacitance measurements on a semiconductor double-quantum dot (DQD) to study tunneling dynamics. By applying phase-tunable high-frequency signals independently to the DQD and a nearby quantum-point-contact charge detector, we perform on-chip lock-in detection of the capacitance associated with the single-electron motion over a wide frequency range from hertz to a few ten gigahertz. Analyzing the phase and the frequency dependence of the signal allows us to extract the characteristic tunneling rates. We show that, by applying this technique to the interdot tunnel coupling regime, quantum capacitance reflecting the strength of the quantum-mechanical coupling can be measured.
Abstract: Direct current and alternating current characteristics of three-terminal nanojunctions (TTJs) are studied at room temperature. The TTJs are based on a modulation-doped GaAs∕AlGaAs heterostructure and were structured by applying mask techniques and wet chemical etching. Devices with lateral dimensions of a few tens of nanometers and with narrow gold contacts were fabricated and transistor characteristics with maximum transconductance values exceeding 100μA∕V are demonstrated. By analyzing the scattering parameters of the TTJs, power gain up to 1.5GHz is observed. This gigahertz amplification is related to the implemented narrow gold contacts which control the quantum capacitance of the electron reservoirs.
13 Nov 2009
TL;DR: In this paper, an analytical model of a nanoscale FET based on epitaxial graphene on SiC was presented, and the achievable performance in the case of fully ballistic transport was evaluated.
Abstract: Epitaxial graphene on SiC substrate is a promising channel material for FETs because it can possibly overcome two main problems of graphene-based devices: the fabrication process is suitable for large-volume manufacturing, and the material exhibits an appreciable semiconducting gap of 0.26 eV. We present an analytical model of a nanoscale FET based on epitaxial graphene on SiC, and assess the achievable performance in the case of fully ballistic transport. Our model also allows us to conduct an exploration of the design parameter space. We observe that the main aspect undermining the performance of graphene FETs on SiC is the still limited energy gap, that has two main consequences: on the one hand it allows band-to-band tunneling at the drain side when the device is in the off state, therefore limiting the achievable I on /I off ratio; on the other hand the injection of holes in the channel, when the device is biased in subthreshold, increases the channel quantum capacitance and can severely degrade the subthreshold slope. We show that an I on /I off ratio of 60 and a subthreshold slope of 150 mV/decade are obtained for a ballistic device without lateral confinement and for a supply voltage of 0.25 V. We also show that performance can be largely improved if accumulation of holes in the channel is inhibited or suppressed ( by allowing a limited degree of inelastic scattering) up to a very interesting I on /I off ratio close to 104.
Proceedings Article•
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TL;DR: In this article, the advantages of nanowires in particular for RF applications are discussed emphasizing the critical role of the quantum capacitance for the device operation, and the authors argue that the one-dimensional character of a nanowire is the key enabler for device operation.
Abstract: Nanowires are an ideal choice for electronic applications. The underlying reason is that they offer a number of intrinsic properties that make them uniquely suited for low-power applications that require a highly linear device response. In this article we discuss the advantages of nanowires in particular for RF applications emphasizing the critical role of the quantum capacitance for the device operation. We argue that the one-dimensional character of a nanowire is the key enabler for device operation in the quantum capacitance limit and the main reason for a vastly different switching behavior in nanowire field-effect transistors.
01 Dec 2009
TL;DR: In this article, a self-consistent atomistic simulation is performed to explore the possibility of boosting the ballistic on-current of the GNRFET by using the experimentally accessible multilayer GNR, which provides a natural structure for 3D stacking of the transistor channel.
Abstract: The graphene nanoribbon (GNR) transistor suffers from the problem of a low on-current due to the nanometer-wide channel. In this work, a self-consistent atomistic simulation is performed to explore the possibility of boosting the ballistic on-current of the GNRFET by using the experimentally accessible multilayer GNR, which provides a natural structure for 3D stacking of the transistor channel. The effects of the number of graphene layers and interlayer coupling strength are studied under different gating technologies. Only limited improvement of the on-current can be achieved with a typical bottom gate because of the small gate insulator capacitance. With a high-к gate, the improvement of the multilayer channel, however, is significant. Reducing the interlayer coupling can further increase the on-current by a factor of 2 for a 5-layer GNR channel.
18 Mar 2009
TL;DR: In this paper, the impact of series resistance on mobility extraction in conventional and recessed-gate n-MOSFETs is investigated, and a specific MOSFLET design that includes additional channel contacts and recended gate technology is used to successfully extract mobility down to 0.9 nm silicon film thickness (4 atomic layers).
Abstract: In this abstract, the impact of series resistance on mobility extraction in conventional and recessed-gate ultra thin body (UTB) n-MOSFETs is investigated. High series resistance leads to an overestimation of the internal source / drain voltage and influences the measurement of the gate to channel capacitance. A specific MOSFET design that includes additional channel contacts and recessed gate technology are used to successfully extract mobility down to 0.9 nm silicon film thickness (4 atomic layers). Quantum mechanical effects are found to shift the threshold voltage and degrade mobility at these extreme scaling limits.
01 Dec 2009
TL;DR: In this paper, the quantum magneto-capacitance of metal-insulator-semiconductor (MIS) structures based on diluted magnetic semiconductors (DMS) in the presence of Rashba spin-orbit interaction (SOI) was investigated.
Abstract: Quantum capacitance has an important role in nanoscale device modelling In the present paper, we investigate the quantum magneto-capacitance of metal-insulator-semiconductor (MIS) structures based on diluted magnetic semiconductors (DMS) in the presence of Rashba spin-orbit interaction (SOI) Typical beating patterns with well defined node-positions in the oscillating quantum capacitance are observed A simple relation that predicts the positions of nodes in the beating patterns is obtained The interplay between the giant Zeeman splitting (including s-d exchange interaction) and the Rashba SOI, is discussed
TL;DR: In this article, a comparative study between the local capacitance of pristine and irradiated graphene is presented, showing that lateral variations in irradiated carbon monolayers are distinctly higher.
Abstract: Irradiation with high energy (500 keV) C+ ions at fluences from 11013 to 11014 cm-2 was used to introduce controlled amounts of defects in single layers of graphene deposited on a SiO2(100 nm)/n+Si substrate. Scanning Capacitance Spectroscopy (SCS) was used as non-destructive characterization technique to probe the effect of irradiation on the electrical properties of graphene. In particular, a comparative study between the local capacitance of pristine graphene and irradiated graphene is presented, showing that lateral variations in irradiated graphene are distinctly higher. The local quantum capacitance per unit area C’q of graphene was extracted from raw data. While a narrow distribution of C’q values was obtained in pristine graphene, two distinct distributions were obtained in irradiated monolayers, associated to locally damaged and not damaged regions, respectively.
TL;DR: In this article, the effects of strong transverse confinement on cylindrical nanowire (NW) gate-all-around MOS were studied using a Schrodinger-Poisson simulator with full-quantum treatment.
Abstract: The effects of strong transverse confinement on cylindrical nanowire (NW) gate-all-around MOS are studied using a Schrodinger-Poisson simulator with full-quantum treatment. This letter is the first to show numerically that the gate capacitance oscillates toward the geometric limit as the gate voltage increases in the inversion regime for a n-type NW MOS; such oscillations are observed at a low temperature range of 5 K-38 K for an NW radius of 5-8 nm. These oscillating capacitance-voltage characteristics are the direct results of the severe nonuniformity of the electron density of states. In contrast to previous works that used semiclassical or quantum correction approaches, this letter demonstrates that full-quantum treatment is needed to observe these capacitance oscillations.
Proceedings Article•
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TL;DR: In this article, the advantages of nanowires in particular for RF applications are discussed emphasizing the critical role of the quantum capacitance for the device operation, and the authors argue that the one-dimensional character of a nanowire is the key enabler for device operation.
Abstract: Nanowires are an ideal choice for electronic applications. The underlying reason is that they offer a number of intrinsic properties that make them uniquely suited for low-power applications that require a highly linear device response. In this article we discuss the advantages of nanowires in particular for RF applications emphasizing the critical role of the quantum capacitance for the device operation. We argue that the one-dimensional character of a nanowire is the key enabler for device operation in the quantum capacitance limit and the main reason for a vastly different switching behavior in nanowire field-effect transistors.
01 Nov 2009
TL;DR: In this paper, a new technique for tuning the oscillation frequency of the VCO was presented, which achieved wide tuning by utilizing a quantum dot transistor as a tunable capacitor.
Abstract: This paper presents a new technique for tuning the oscillation frequency of the VCO. The proposed VCO technique accomplishes wide tuning by utilizing a quantum dot transistor as a tunable capacitor. The capacitance of the quantum dot transistor is changed by controlling the quantum dot charges that lead to varying the threshold voltage. The results show that a wide oscillation frequency range is achieves. The oscillation frequency is tuned from 19.13 GHz to 27.18 GHz, tuning of 42%, as the quantum dot transistor threshold shift varies by 0.7 V.
01 Dec 2009
TL;DR: In this paper, the authors investigated the electrical characteristics of silicon nanowire transistors using a fully ballistic quantum mechanical transport approach to analyze rectangular silicon nano-wire transistor and investigated the impact of structural parameters of nano-scale gate all around silicon nano wire transistor (GAA-SNWT) on its electrical characteristics in sub-threshold regime.
Abstract: In this paper we investigate the electrical characteristics of silicon nanowire transistors using a fully ballistic quantum mechanical transport approach to analyze rectangular silicon nanowire transistor We investigate the impact of structural parameters of nano scale Gate all around Silicon nano wire transistor (GAA-SNWT)on its electrical characteristics in subthreshold regime In particular we show that increase in Source/Drain length (L S , L D ) negligibly affects the current while increasing the L S /L D will affect the gate capacitance We also investigate the effect of increasing the gate underlap on short channel effects and on the switching speed of device We show that if the L un is increased the gate capacitance and DIBL will reduces while the I ON /I OFF ratio is increased This parameter affect the power consumption and delay and is useful in nanowire design for low power application
TL;DR: In this paper, the authors investigate doping of a single-layer graphene in the presence of electrolytic top gating and demonstrate the sensitivity of graphene's doping levels to the salt concentration and the importance of quantum capacitance that arises due to the smallness of the Debye screening length in the electrolyte.
Abstract: We investigate doping of a single-layer graphene in the presence of electrolytic top gating. The interfacial phenomena is modeled using a modified Poisson-Boltzmann equation for an aqueous solution of simple salt. We demonstrate both the sensitivity of graphene's doping levels to the salt concentration and the importance of quantum capacitance that arises due to the smallness of the Debye screening length in the electrolyte.