Quantum capacitance

About: Quantum capacitance is a research topic. Over the lifetime, 954 publications have been published within this topic receiving 24165 citations.

Energetic and capacitive parameters of few-layer graphene decorated with transition metal oxide Co3O4

Abstract: Sandwich-like composite on the base of graphene and Co3O4 nanocubes is a prospect material for electrodes of chemical sources of current. The total capacitance of this material is mainly contributed by quantum capacitance that depends on a change of Fermi level during charge/recharge cycles. The main goal of this paper is to calculate the dependence of Co3O4@graphene’s quantum capacitance on mass ratio of its components. The obtained results can be applied in the design of modern supercapacitors and lithium-ion batteries.

Tunnel field effect transistor on a quantum well formed by three layers of graphene derivatives (COH)n-(CF)n-(CH)n, with the drain from the middle layer - (CF)n

Abstract: In the paper the version of the field effect tunnel nano transistor on quantum well is researched, where the control voltage is applied to the barriers surrounding the quantum well, and electron drain comes from the quantum well. Electrons tunnel into the quantum well through the first half of the two-humped tunnel barrier (double heterojunction) formed by the sandwich of three layers of wide band 2D semiconductors (graphene derivatives: perhydrooxy grafen (COH)n, fluoro graphen (CF)n, grafan (CH)n) essentially differing in locations of the bottom level of the conduction band. The middle layer - fluoro graphen (CF)n has the lowest bottom of the conduction band, which forms the quantum well with depth of ~ 3 eV and a width of ~ 0.6 nm in the total tunnel potential barrier of 1.8 nm width, and serves as a channel for the flow of electrons. Metal electrode of source and metal electrode of gate adjacent to the outer layers of 2D semiconductor sandwich - perhydrooxy grafen (COH)n and grafan (CH)n, respectively, form the common "gate" of sandwich with size 22*22 nm^2. A metal drain electrode with a width of 10 nm and with the potential on 1 V higher than that of the first electrode (source) are in contact with the middle layer of fluoro graphen (CF)n, beyond of the sandwich having for this purpose the width of 35 nm greater than that of the outer semiconductor layers 2D internal three-layer sandwich. The potential of the gate opening is 0.62 V. The maximum operating current Isd is ~ 2*10^(-5) A. Current flowing in a closed state theoretically is equal to zero, and the parasitic current flowing through the gate electrode in the open state Ig = Ileak is ~ 10^(-10) A. Quantum capacitance of the transistor would allow the device to operate at a frequency of up to 10^12 Hz.

Extrinsic performance of flexible graphene FET with graphene oxide gate dielectric

Abstract: A study is performed on extrinsic performance of graphene field effect transistor on a flexible polyimide substrate with graphene oxide gate dielectric. Using self-consistent calculation, it is shown that quantum capacitance retains a nonzero minimum at the dirac point. Excellent electron and hole mobilities and maximum on current of 137 μA are obtained for this flexible device. RF analysis has shown that it is capable of amplifying input signal with frequency as high as 1.71 GHz. We have demonstrated that graphene field effect transistor shows higher leakage current than conventional transistor.

The impact of structural parameters on the electrical characteristics of GAA Silicon nanowire transistor

Abstract: In this paper we investigate the electrical characteristics of silicon nanowire transistors using a fully ballistic quantum mechanical transport approach to analyze rectangular silicon nanowire transistor We investigate the impact of structural parameters of nano scale Gate all around Silicon nano wire transistor (GAA-SNWT)on its electrical characteristics in subthreshold regime In particular we show that increase in Source/Drain length (L S , L D ) negligibly affects the current while increasing the L S /L D will affect the gate capacitance We also investigate the effect of increasing the gate underlap on short channel effects and on the switching speed of device We show that if the L un is increased the gate capacitance and DIBL will reduces while the I ON /I OFF ratio is increased This parameter affect the power consumption and delay and is useful in nanowire design for low power application