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Quantum capacitance

About: Quantum capacitance is a research topic. Over the lifetime, 954 publications have been published within this topic receiving 24165 citations.


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Proceedings ArticleDOI
17 Oct 2013
TL;DR: In this paper, a new simulation framework for short channel GFETs is introduced, which includes full device electrostatics and physical mechanisms like band-to-band generation-recombination, realistic contact geometry, generalized diffusion, quantum capacitance, and carrier density dependent velocity saturation (vsat).
Abstract: Graphene is a promising candidate for future electronics such as RF transistors, interconnects and flexible components. The simulation and analysis of graphene transistors (GFETs) has so far relied on two approaches: on one hand, compact modeling is efficient but tends to lack physical details and neglects geometric phenomena such as fringing electric fields. On the other hand, atomistic simulations with non-equilibrium Green's functions (NEGF) rigorously account for quantum effects, but phonon scattering is challenging to incorporate realistically, rendering simulation results which are often difficult to compare with experimental data.Here we introduce a new simulation framework better suited for short channel GFETs, which includes the full device electrostatics and physical mechanisms like band-to-band generation-recombination, realistic contact geometry, generalized diffusion, quantum capacitance, and carrier density dependent velocity saturation (vsat).
Proceedings ArticleDOI
05 Mar 2015
TL;DR: In this article, the authors calculate bandgap, energy, quantum capacitance and gate delay by considering strained A-GNR for corresponding source voltage, where the edge effect is considered.
Abstract: Armchair Graphene nanoribbons(A-GNRs) are now widely used in nanoscale transistor because of its semiconducting behavior and fast switching speed. The most important parameter which impedes carrier movement through the channel is “capacitance” after its sustainable value. Earlier classical capacitance was assumed as only one of the capacitance in nanoscale transistor. But when the device is operated by a source; classical capacitance goes in vain for overall observing the carrier statistics. Here another capacitance must be considered which “Quantum capacitance” is. Edge effect which is caused during fabrication for the deviation of true structure. In previous literature, it is quantum capacitance calculated by considering edge effect only .But another phenomena is also appeared when GNR is subjected to a considerable strain in fabrication. In this paper we will calculate bandgap, energy , quantum capacitance and gate delay by considering strained A-GNR for corresponding source voltage.
01 Jan 2013
TL;DR: In this paper, the fabrication and characterization of graphene field effect transistors operating at microwave frequencies was explored and compared to a mono-gated and a double gated FET with the same geometry, dielectric layer thickness and gate length.
Abstract: With the end of Si based Metal Oxide Semiconductor Field Effect Transistor scaling paradigm approaching fast as predicted by the Moore’s Law, and the technological advancements as well as human needs in many ways pushing for faster devices, graphene has emerged as a powerful alternative solution. This is so because of its very special properties like high charge carrier mobility, highly linear dispersion relation, high current carrying capacity and so on. However, since we have a finite resistance at Dirac point, the on/off ratio in graphene devices is sufficiently low, making graphene devices not so suitable for logical applications. At the same time, the 1/f noise, which is understood till now to originate from surface disorders like those observed in a two-dimensional electron gas system like graphene and is a major unwanted outcome in mesoscopic regime devices, reduces very much at high frequencies, making these devices good candidates for high frequency analogue applications. Motivated by these observations, this work explores fabrication and characterization of graphene field effect transistors operating at microwave frequencies, and compares a double gated device performance to a mono-gated device having the same geometry, dielectric layer thickness and gate length. A simple electrostatic finite element simulation model has also been developed to support our experimental observations by fitting simulated gate coupling capacitance values to the measured data. The model helps us in understanding the level of interface trap charge densities introduced into the device channel during fabrication, and the effect of quantum capacitance on device performance, and is in line with the experimental observations. Our results show that a double gated graphene FET has superior performance compared to a mono-gated FET.
Journal ArticleDOI
01 Sep 2023-Vacuum
TL;DR: In this paper , the electronic and optical properties, work function and quantum capacitance of Janus Hf2COT (T = -Br, -Cl, -F, -OH, -P, -S, -Se) MXene are investigated using density functional theory.
Posted ContentDOI
18 Nov 2022
TL;DR: In this paper , a finite element modeling of an EDL-gated field effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in a semiconductor, in which density of states, and therefore, quantum capacitance is included.
Abstract: Electric double layer (EDL) gating can induce large capacitance densities (∼1−10 μF/cm^2) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (VG) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate, and therefore the timescale over which the channel can be doped. Typical thicknesses are on the order of microns, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) both in terms of physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore, quantum capacitance is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied VG without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which VG is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3×10^13 cm^−2 for electrons and 1.4×10^13 cm^−2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, polyethylene oxide (PEO):CsClO_4, is decreased from 1 μm to 10 nm and used to EDL- gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm−1 μm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202238
202162
202062
201965
201858