Showing papers on "RC circuit published in 1993"

Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs

Abstract: A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed. >

Impedance spectroscopy of human erythrocytes: system calibration, and nonlinear modeling

Abstract: The authors present an impedance measurement method, the cell embedding technique, for human erythrocytes, and an accurate calibration procedure for a four-electrode impedance measurement system that gives reliable results over a wide frequency range-1 Hz to 10 MHz. To achieve high sensitivity, the cells are embedded in the pores of a Nuclepore filter. The calibration procedure assumes that the measurement system is linear and require measurement of three reference impedances. The reliability of the procedure is demonstrated with various RC circuits. Its application to the bio-impedance measurement system eliminates a quasi-dispersion in the high-frequency range and increases the bandwidth at both the low- and high-frequency ends of the range by about a decade. The experimental data are fitted to, an equivalent circuit model of the impedance of the embedded cells. The impedance spectra display constant-phase-angle (CPA) characteristics, which are used to describe the AC response of the interface between the cell surface, and the external electrolyte solution. Such a CPA element may be related to fractal character of the interface. >

Nullators and norators in voltage to current mode transformations

Abstract: In this circuit transformation, the short-circuit transfer function of the resulting circuit is then exactly the same as the open-circuit voltage transfer function of the original circuit

A Q-enhanced active-RLC bandpass filter

Abstract: The passive elements R, L, and C are combined with an amplifier to realize a high-Q bandpass filter. Positive feedback is used to enhance the finite Q of the lossy integrated inductors, and design equations are given that take into account the finite gain and finite bandwidth of the amplifier. It is shown that a quality factor of 20 at 1 GHz is possible with 10-GHz transistors. Preliminary noise analysis indicates promising results. >

Current output type d/a converter circuit

Abstract: PURPOSE: To set the variable range of the output current optional by connecting a reference current source to a 1st current mirror circuit, using an output of a 1st amplifier for a reference potential application point and giving 1st to n-th outputs of a 2nd current mirror circuit to n-sets of weighting terminals of an R-2R resistor ladder circuit. CONSTITUTION: A current of a reference current source 1 is given to a 1st current mirror circuit comprising transistors(TRs) 2-3 and resistors 5-7, its 1st output is inputted to a current-voltage circuit comprising a resistor 9 and an amplifier 8, in which the output is converted into a voltage and it is used for a reference voltage for an R-2R ladder circuit comprising resistors 24-29. A 2nd output of the 1st current mirror circuit is given to a 2nd current mirror circuit having n-sets of outputs comprising TRs 10-14 and resistors 15-19 and n-sets of outputs are given to n-sets of control current terminals to the R-2R resistor ladder circuit via switches 20-23 to decide an output voltage of the R-2R resistor ladder circuit. COPYRIGHT: (C)1994,JPO

Wideband (DC to GHz) balun

Abstract: An ultra wide band DC to GHz balun consisting of transmission lines, a small inverting junction, and an RC network connecting the shields of the balanced load transmission lines such that an unbalanced source sees a matched load from DC to GHz.

Charge/discharge control circuit.

Abstract: PROBLEM TO BE SOLVED: To stop discharge before a switching circuit generates heat and breaks down, by performing discharge control receiving the signals of a circuit which detects two kinds or more of different voltages of overcurrent detecting terminals, and exhibiting a discharge stopping function by an appropriate delay time, against two kinds or more of different load currents. SOLUTION: The reference voltage 111 of a reference voltage circuit 105 is set higher than the reference voltage 112 of a reference voltage circuit 106, and the delay time of a delay circuit 109 is set shorter than that of a delay circuit 110. By performing setting this way, a switching circuit 103 is turned off after the delay time preset by the delay circuit 110, when an overcurrent flows and the voltage of a current sensing resistor 104 is kept higher than the reference voltage 112 and lower than the reference voltage 111. Accordingly, it becomes possible to turn the switching circuit off by a shorter delay time than the switching circuit generates heat and breaks down, even if something abnormal happens and an excessive current flows. COPYRIGHT: (C)1998,JPO

Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures

Abstract: An approach to computing the time response of an arbitrary 3-D interconnect structure based on asymptotic waveform evaluation (AWE) is introduced. It has been implemented in a software tool called 3DAWE. To facilitate the application of AWE to a 3D RC mesh network model, the AWE formulation is rederived based on a nodal analysis approach. The ICCG matrix solver has been successfully applied in 3DAWE. It is shown that the typical transient response of a reasonably large 3D RC network can be obtained within a few minutes on a 15-MIPS computer using this program. >

Methods of self-calibration for a key-type mouse

Abstract: This invention relates to methods of self-calibration for computer display cursor positioning devices imbedded within a computer keyboard key (sometimes referred to herein as a "key-type mouse") or other pointing device. A plurality of Force Sensitive Resistor grids ("FSRs") or other pressure sensitive sensors are used to detect relative pressure applied in various directions to a predetermined key of a computer keyboard. An RC circuit is used to indirectly read the values of the FSRs. A predetermined delay period is associated with each sensor followed by a measurement period. The resistance of the FSR is related to the measurement period taken to reach a given voltage value after the predetermined delay period. A positive or negative offset to the predetermined delay period adjusts the time necessary for the RC circuit to reach a predetermined bias voltage value. By breaking the charging time into a delay period and a measurement period the amount of time that the keyboard controller or microprocessor must spend devoted to watching the voltage across the RC circuit for the moment when it reaches VCC is reduced, improving the operation of the keyboard.

Charge-balanced switched-capacitor circuit and amplifier circuit using same

Abstract: A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Circuit for introducing hysterisis

Abstract: A novel driver circuit and feedback loop is provided that improves the response time of the driver circuit and produces threshold voltages and hysteresis levels which are substantially independent of the supply voltage. The feedback circuit uses a pair of transistors connected in a cascode configuration to provide positive feedback from the output of the driver circuit and to control this feedback by means of the signal at the driver circuit input. By coupling the input voltages to the gate of a cascode transistor, the response time of the driver circuit is improved without disturbing its high input impedance. In addition, by replacing a transistor in the driver circuit input buffer with a current source, the threshold voltage of the driver circuit can be made substantially independent of the supply voltage.

Current-sensing power-on reset circuit for integrated circuits

Abstract: The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

Circuit and method for protecting power components against forward overvoltages

Abstract: A circuit protects a power transistor of the vertical MOS or IGTB-type during the off state against forward overvoltages. The protection circuit includes a first circuit for limiting the voltage across the transistor to a predetermined voltage, lower than the forward breakdown voltage of the power transistor, a circuit for detecting the quantity of energy dissipated in the transistor when the first circuit is enabled, and a second circuit for turning the transistor on at low impedance. The second circuit is enabled when the detection circuit has detected that the dissipated energy has exceeded a predetermined energy threshold.

Adaptive RC product control in an analog-signal-manipulating circuit

Abstract: An integrated circuit includes an analog-signal manipulating circuit (ASMC) such as a filter having a transfer function with a frequency response that is determined by at least one RC product. The integrated circuit also includes separately an RC oscillator. The frequency-response-determining RC products of an RC component pair in the filter and an oscillator frequency determining RC component pair in the RC oscillator are digitally programmable by an external microprocessor. The microprocessor holds the frequency of the RC oscillator fixed relative to its own crystal controlled oscillator by adjusting the programmable RC component pair of the RC oscillator. The same adjusting digital signal from the microprocessor is simultaneously applied to the programmable RC component pair(s) of the ASMC, which has the effect of stabilizing all RC component pairs and thus the ASMC frequency response. The capacitors of each RC component pair have binary-control-signal lines mutually parallel connected to each other. The microprocessor senses the frequency of the oscillator and by sending the appropriate binary control signal to the paralleled control lines to adjust the frequency of the RC oscillator to a predetermined value, the RC products of the other component pairs in the filter are adjusted to their respective predetermined values and maintained there during operation of the integrated filter circuit while subject to changes in temperature that would otherwise alter the RC products and therefore the transfer function of the ASMC.

Active surge rejection circuit.

Abstract: The ACTIVE SURGE REJECTION CIRCUIT uses a FET connected in one of the TIP and RING leads to open and close the lead. A JK flip-flop is connected to a voltage sensing circuit which senses voltage surges and clocks the flip-flop early in the voltage rise. This activates a first circuit to ground the FET gate and hold the FET open. Meanwhile, a second circuit comprising an RC circuit charges a capacitor which maintains the FET in its OFF condition for a period of time longer than the surge, i.e., about 1 m sec, and then clears the JK flip-flop after the capacitor has discharged a predetermined amount. This invention thus provides surge (noncommon mode) protection, and is especially useful in protecting modems from voltage surges while minimizing signal distortion during non-surge conditions.

Frequency-stabilised RC oscillator for clock generator circuit

Abstract: The oscillator has an ohmic load (R11) and at least one capacitor (C1) determining the oscillation frequency, with a current sink (1) providing a constant current (Ik) in dependence on the ohmic load and a reference voltage (Uref), controlling the charging current circuit (2) for the capacitor. At least one comparator (3, 5) compares the capacitor voltage with the reference voltage, to control a discharge circuit (4) for the capacitor. Pref. the charging current circuit delivers a constant charging current to 2 capacitors (C1, C2) each capacitor voltage compared with the reference voltage by a respective comparator, with corresponding control of the capacitor charging and discharging cycles, one capacitor charged as the other is discharged.

Power-on reset circuit responsive to a clock signal

Abstract: A power-on reset circuit includes a differentiator circuit, a sample-hold circuit and a reset signal generating circuit. The differentiator circuit differentiates a clock signal from an oscillator after a power supply is applied to a power supply terminal. The sample-hold circuit samples a power component only from the output of the differentiator circuit. When the power component exceeds a threshold voltage of the reset signal generating circuit, the reset signal generating circuit generates and provides a reset signal for a logic circuit during a certain period.

Rate of change comparator

Abstract: A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circuit charges quickly through its diode but discharges slowly through its resistor and the discharging circuit discharges quickly through its diode and slowly through its resistor. The difference in output between the charging and discharging circuits is detected with a comparator, biased off by a threshold bias voltage developed from one of the circuits. The comparator is unaffected by slow changes in transducer signals due to drift, ambient condition and similar changes because the differential voltage between the circuits is minimized for transducer signal changes below the level set by a threshold bias level. When the transducer signal is positive and the rate of change of the transducer signal exceeds the minimum rate of change set by the RC time constant of the discharging circuit, the diode allows the charging circuit to charge faster than the discharging circuit and the differential voltage therebetween triggers the comparator to indicate that an event was detected if the differential voltage exceeds the threshold bias voltage. Similarly, when the transducer signal is negative and the rate of change of the transducer signal exceeds the minimum rate of change set by the RC time constant of the charging circuit, the diode allows the discharging circuit to discharge faster than the charging circuit and the differential voltage therebetween triggers the comparator to indicate that an event was detected if the differential voltage exceeds the threshold bias voltage.

Voltage mode pulse width modulation controller

Abstract: A pulse width modulator voltage feedforward circuit which includes a gating circuit for providing a control signal to a charge circuit which charges an integration circuit with a current proportional to an input voltage. The integration circuit provides an output ramp signal waveform having a slope proportional to the input voltage value. The gating circuit also provide a control signal to a discharge circuit, to thus alternately charge and discharge the integration circuit. The gating circuit insures that a minimum deadtime for a transformer reset will occur regardless of input voltage variations by preventing a fixed frequency signal provided by an oscillator from beginning a new ramp waveform signal period until the integration circuit is discharged to a minimum reference voltage level.

Timed-off control apparatus and method

Abstract: An improved timed-off control apparatus and method are provided to prevent excessive cycling of an electrically operated device, such as an air conditioning compressor. The timed-off control apparatus provides a predetermined timed-off period (e.g., five minutes), during which the electrically operated device is constrained to remain in an off state after the device is deactivated by a loss of power. For example, in an air conditioning system, fluctuations in power supply voltage and thermostat switch bounces may result in excessive cycling of the system compressor. By constraining the compressor to remain deactivated for the selected timed-off period, the compressor is protected against excessive cycling. In order to achieve consistent and predictable timed-off periods, a field effect transistor (FET) is used in conjunction with a resistance/capacitance (RC) circuit. When the power supply is interrupted, the FET is turned off state and remains off during the timed-off period. When the FET is off, the compressor remains off, even if electrical power becomes available during the timed-off period. The FET monitors the voltage across the capacitor of the RC circuit while the capacitor is being discharged and when the voltage drops below a predetermined threshold, the FET is turned on to allow resumption of compressor operation. The time at which the voltage across the capacitor reaches the predetermined threshold is a function of the capacitor discharge rate. Because the FET does not draw biasing current, the capacitor discharge rate is not affected by the FET. Therefore, consistent and predictable timed-off periods are achieved.

Sample and hold circuit and finite impulse response filter constructed therefrom

Abstract: A high speed sample and hold circuit comprises an amplifier for producing an output current which is a linear function of an input voltage. A capacitor is responsive to the output current for producing an output voltage representative of the integral of the output current over a predetermined period of time. A switch selectively connects the amplifier to the capacitor during the predetermined period of time. A circuit for discharging the capacitor is also provided. A circuit for producing clock pulses controls the operation of the switch and the discharge circuit. A finite impulse response filter may be constructed around the sample and hold circuit.

Delay prediction from resistance-capacitance models of general MOS circuits

Abstract: Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented. >

High power factor circuit for powering a load

Abstract: A power supply circuit with a high power factor includes circuitry for receiving an a.c. voltage from an a.c. power source supplying a.c. input current, and circuitry for generating a rectified voltage from the a.c. voltage. The circuit further includes a filter network coupled to the rectifier circuitry for receiving the rectified voltage and, in response, providing a filtered voltage for powering a load. The filter network comprises at least first and second filter capacitors, first circuit circuitry for placing the filter capacitors in series when the capacitors are being charged from the rectified voltage, and second circuit circuitry for placing each capacitor in a respective parallel discharge path when the capacitors are discharging energy into the load. The first circuit circuitry of the filter network includes a resistor with a resistance value selected to reduce harmonic distortion of the a.c. input current to such an extent that the power factor of the circuit exceeds about 90 percent. The load for the mentioned power supply circuit preferably comprises a low pressure discharge lamp contained within a resonant ballast circuit, and a half-bridge switching network for supplying bi-directional power to the resonant ballast circuit.

Digital-to-analog converter with reference glitch reduction

Abstract: A analog-to-digital converter (DAC) comprises a plurality of circuit stages. Each of the circuit stages includes a switching circuit having an assertive circuit portion and a complementary circuit portion. A first transistor and a first resistor constitute the assertive circuit portion, which is electrically connected between a first reference voltage supply conductor and a switch output node inside the DAC. In a similar fashion, a second transistor and a second resistor constitute the complementary circuit portion, which is also electrically connected between a second reference voltage supply conductor and the switch--output node. The first and second resistors, and the resistor in the resistor network which is electrically connected to the switch output node, are substantially equal in ohmic values. Thus, when one of the circuit portions is active and the other circuit portion is inactive, the corresponding resistor in the active circuit portion operates as a part of the resistor network to provide a voltage division between the first and second reference voltage supply conductors. However, when both of the circuit portions are active, the first and second resistors operate together as a current limiting circuit to prevent an excess current surge between the first and second reference voltage supply conductors.

Level shifting low to high supply voltage interface circuit

Abstract: When the input signal IN1 changes from a ground voltage GND to a first voltage -E1 and from the first voltage -E1 to the ground voltage GND, the output potential of the -E2 system flip-flop circuit changes gradually. The inverted signal from the -E1 system inverter circuit is supplied to the -E2 system inverter circuit earlier than the output signal (high-potential signal) of the -E2 system flip-flop circuit. This eliminates a period of time when all the MOSFETs in the -E2 system inverter circuit turn on simultaneously, thereby reducing a through current in the -E2 system inverter circuit. Consequently, the circuit operation can be stabilized by decreasing through currents flowing in the -E1 system inverter circuit and the -E2 system inverter circuit using the output signal of the -E2 system flip-flop circuit as an input.

Constant-current power-supply circuit formed on an IC

Abstract: There are provided a first constant-current circuit and a second constant-current circuit, and a first resistor connected in series with the first constant-current circuit generates a band-gap voltage. The first constant-current circuit and the second constant-current circuit constitute a current Miller circuit, and a part of a current that flows through the second resistor connected in series with the second constant-current circuit is outputted as a constant current source. The constant-current power supply IC, which has the above-mentioned arrangement, is designed as follows: the first resistor and the second resistor have a predetermined line-width ratio that is determined in such a manner that if the respective line-widths vary by virtually the same value, a varied amount in the second constant current value that has been caused by a variation in the value of resistivity of the first resistor is cancelled by a varied amount caused by a variation in the value of resistivity of the second resistor. This arrangement is effective in compensating function and makes it possible to minimize the error on the constant current output due to deviations that occur during production.