Showing papers on "RC circuit published in 1996"
Book•
30 Dec 1996TL;DR: In this paper, the authors present an overview of electrical circuits and their properties, including inductance, capacitance, and capacitance in series and parallel, as well as an analysis of a simple NMOS Amplifier.
Abstract: (NOTE: Each chapter concludes with Summary and Problems.) I. CIRCUITS. 1. Introduction. Overview of Electrical Engineering. Circuits, Currents, and Voltages. Power and Energy. Kirchhoff's Current Law. Kirchhoff's Voltage Law. Introduction to Circuit Elements. Introduction to Circuits. 2. Resistive Circuits. Resistances in Series and Parallel. Network Analysis by Using Series and Parallel Equivalents. Voltage-Divider and Current-Divider Circuits. Node-Voltage Analysis. Mesh-Current Analysis. Thevenin and Norton Equivalent Circuits. Superposition Principle. Wheatstone Bridge. 3. Inductance and Capacitance. Capacitance. Capacitances in Series and Parallel. Physical Characteristics of Capacitors. Inductance. Inductances in Series and Parallel. Practical Inductors. Mutual Inductance. 4. Transients. First-Order RC Circuits. DC Steady State. RL Circuits. RC and RL Circuits with General Sources. Second-Order Circuits. 5. Steady-State Sinusoidal Analysis. Sinusoidal Currents and Voltages. Phasors. Complex Impedances. Circuit Analysis with Phasors and Complex Impedances. Power in AC Circuits. Thevenin and Norton Equivalent Circuits. Balanced Three-Phase Circuits. 6. Frequency Response, Bode Plots, and Resonance. Fourier Analysis, Filters, and Transfer Functions. First-Order Lowpass Filters. Decibels, the Cascade Connection, and Logarithmic Frequency Scales. Bode Plots. First-Order Highpass Filters. Series Resonance. Parallel Resonance. Ideal and Second-Order Filters. Digital Signal Processing. II. DIGITAL SYSTEMS. 7. Logic Circuits. Basic Logic Circuit Concepts. Representation of Numerical Data in Binary Form. Combinatorial Logic Circuits. Synthesis of Logic Circuits. Minimization of Logic Circuits. Sequential Logic Circuits. 8. Microcomputers. Computer Organization. Memory Types. Digital Process Control. The Motorola 68HC11/12. The Instruction Set and Addressing Modes for the 68HC11. Assembly-Language Programming. 9. Computer-Based Instrumentation Systems. Measurement Concepts and Sensors. Signal Conditioning. Analog-to-Digital Conversion. LabVIEWaA A . III. ELECTRONICS. 10. Diodes. Basic Diode Concepts. Load-Line Analysis of Diode Circuits. Zener-Diode Voltage-Regulator Circuits. Ideal-Diode Model. Piecewise-Linear Diode Models. Rectifier Circuits. Wave-Shaping Circuits. Linear Small-Signal Equivalent Circuits. 11. Amplifiers: Specifications and External Characteristics. Basic Amplifier Concepts. Cascaded Amplifiers. Power Supplies and Efficiency. Additional Amplifier Models. Importance of Amplifier Impedances in Various Applications. Ideal Amplifiers. Frequency Response. Linear Waveform Distortion. Pulse Response. Transfer Characteristic and Nonlinear Distortion. Differential Amplifiers. Offset Voltage, Bias Current, and Offset Current. 12. Field-Effect Transistors. NMOS and PMOS Transistors. Load-Line Analysis of a Simple NMOS Amplifier. Bias Circuits. Small-Signal Equivalent Circuits. Common-Source Amplifiers. Source Followers. CMOS Logic Gates. 13. Bipolar Junction Transistors. Current and Voltage Relationships. Common-Emitter Characteristics. Load-Line Analysis of a Common-Emitter Amplifier. pnp Bipolar Junction Transistor. Large-Signal DC Circuit Models. Large-Signal DC Analysis of BJT Circuits. Small-Signal Equivalent Circuits. Common-Emitter Amplifiers. Emitter-Followers. 14. Operational Amplifiers. Ideal Operational Amplifiers. Summing-Point Constraint. Inverting Amplifiers. Noninverting Amplifiers. Design of Simple Amplifiers. Op-Amp Imperfections in the Linear Range of Operation. Nonlinear Limitations. DC Imperfections. Differential and Instrumentation Amplifiers. Integrators and Differentiators. Active Filters. IV. ELECTROMECHANICS. 15. Magnetic Circuits and Transformers. Magnetic Fields. Magnetic Circuits. Inductance and Mutual Inductance. Magnetic Materials. Ideal Transformers. Real Transformers. 16. DC Machines. Overview of Motors. Principles of DC Machines. Rotating DC Machines. Shunt-Connected and Separately Excited DC Motors. Series-Connected DC Motors. Speed Control of DC Motors. 17. AC Machines. Three-Phase Induction Motors. Equivalent Circuit and Performance Calculations for Induction Motors. Synchronous Machines. Single-Phase Motors. Stepper Motors. Appendix A: Complex Numbers. Appendix B: Nominal Values and the Color Code for Resistors. Appendix C: Preparing for the Fundamentals of Engineering Exam. Appendix D: Computer-Aided Circuit Analysis. Index.
195 citations
TL;DR: This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure and generates a linear equivalent gate model which accurately captures the delays at the interconnect fan-out nodes.
Abstract: For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure. The delay and power are calculated with errors on the same order as those for the original empirical equations. Moreover, a linear equivalent gate model is generated which accurately captures the delays at the interconnect fan-out nodes.
172 citations
Patent•
20 Jun 1996
TL;DR: In this article, an integrated circuit controller for power factor correction circuit that provides unity power factor by sensing only a current in the PFC and a dc supply voltage is proposed, which is coupled to a circuit for generating the DC supply voltage.
Abstract: An integrated circuit controller for power factor correction circuit that provides unity power factor by sensing only a current in the power factor correction circuit and a dc supply voltage. The power factor correction circuit is coupled to a circuit for generating the dc supply voltage. Thus, the dc supply voltage is representative of the regulated output voltage of the power factor correction circuit. The dc supply voltage is sensed and integrated over each clock cycle and compared to an inverted and amplified version of the sensed current for controlling operation of the power factor correction circuit. By sensing the dc supply voltage, rather than the output voltage of the power factor correction circuit, the integrated circuit requires fewer pins. In a preferred embodiment, the integrated circuit also includes a pulse width modulation controller circuit. Because a single clock signal is utilized for performing both leading edge modulation in the power factor correction circuit and trailing edge modulation in the pulse width modulation circuit, fewer pins are required. Therefore, the integrated circuit controls the power factor correction circuit and the pulse width modulation circuit while being contained within an eight-pin integrated circuit.
114 citations
01 Jun 1996
TL;DR: This work develops a provably stable two pole transfer function/impedance model based on the first three moments of the impulse response that will be an effective metric for high speed interconnect circuit models.
Abstract: Due to its simplicity, the ubiquitous Elmore delay, or first moment of the impulse response, has been an extremely popular delay metric for analyzing RC trees and meshes. Its inaccuracy has been noted however and it has been demonstrated that higher order moments can be mapped to dominant pole approximations (e.g. AWE) in the general case. The first three moments can be mapped to a two pole approximation, but stability is an issue and even a stable model results in a transcendental equation that must be iteratively evaluated to determine the delay. We describe an explicit delay approximation based on the first three moments of the impulse response. We begin with the development of a provably stable two pole transfer function/impedance model based on the first three moments (about s=0) of the impulse response. Then, since the model form is known, we evaluate the delay (any waveform percentage point) in terms of an analytical approximation that is consistently within a fraction of 1 percent of the "exact" solution for this model. The result is an accurate, explicit delay expression that will be an effective metric for high speed interconnect circuit models.
98 citations
Patent•
12 Sep 1996
TL;DR: In this paper, a hardness measuring apparatus with a frequency deviation detecting circuit is described. But the circuit is not a self-oscillating circuit and the gain variation compensating circuit has a central frequency different from that of the self oscillator and increases gain in response to a change in frequency.
Abstract: A hardness measuring apparatus in which a frequency deviation detecting circuit is used has a contact element, an oscillator, a self-oscillating circuit and a gain variation compensating circuit. The self-oscillating circuit feeds back oscillation information of the oscillator to generate a resonant state. The gain variation compensating circuit is disposed in the self-oscillating circuit. The gain variation compensating circuit has a central frequency different from that of the self-oscillating circuit, and increases gain in response to a change in frequency.
86 citations
12 May 1996
TL;DR: In this article, a delay and power model of a CMOS inverter driving a resistive-capacitive load is presented, which is derived from Sakurai's alpha power law and exhibits good accuracy.
Abstract: A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha power law and exhibits good accuracy. The model can be used to design and analyze those inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay, transition time, and short circuit power dissipation for a CMOS inverter driving resistive-capacitive interconnect lines.
72 citations
08 Feb 1996
TL;DR: In this paper, a fully-integrated dual (I and Q) low-pass seventh-order Chebychev continuous-time filters for IS-95 CDMA channel selection applications are presented.
Abstract: This paper presents fully-integrated dual (I and Q) low-pass seventh-order Chebychev continuous-time filters for IS-95 CDMA channel selection applications. The capabilities of digital signal processors, available in almost all modern transceivers, are exploited to adapt the filter bandwidth to the desired frequency with minimum additional hardware. To fulfill the requirement of handling signals with a wide dynamic range, an active RC filter topology is adopted. Digital tunability is provided by constructing each integrating capacitor with an array of binary-weighted capacitors. The capacitors are switched in or out under the control of the DSP. The ratio of the fixed capacitor to the total variable capacitors is chosen based on the expected RC time-constants variations.
72 citations
TL;DR: In this paper, a hysteresis chaos generator is proposed, which consists of two capacitors, two resistors, one linear VCCS and one hystresis VCCs.
Abstract: A novel and extremely simple design of a hysteresis chaos generator is proposed. The circuit consists of two capacitors, two resistors, one linear VCCS and one hysteresis VCCS. The two VCCSs are implemented by using OTA and realize stretching and folding mechanism for chaos generation.
71 citations
Patent•
26 Jun 1996TL;DR: In this article, a mixer circuit with inductive elements for low voltage applications is presented, which consists of a balanced amplifier and a switch composed of transistor pairs driven by a local oscillator signal.
Abstract: A mixer circuit is provided which incorporates inductive elements for low voltage applications. The circuit consists of a balanced amplifier and a switch composed of transistor pairs driven by a local oscillator signal for multiplying the signal to produce a circuit output signal having a predetermined intermediate frequency. Inductors are used to provide degenerative feedback in the balanced amplifier portion of the circuit. The inductors generate negligible noise and produce a negligible dc voltage drop. The transistors in the circuit are thereby maintained in saturation regions of operation as desired. In accordance with another aspect of the invention, an inductor or, alternatively, a parallel inductor-capacitor circuit, is used as a constant current source in conjunction with the input transistors in the balanced amplifier portion of the circuit.
71 citations
TL;DR: In this paper, a novel configuration is presented which can realize single-resistance controlled active-RC and active-R oscillators and low-pass/band-pass filters from the same structure.
Abstract: A novel configuration is presented which can realize single-resistance controlled active-RC and active-R oscillators and low-pass/band-pass filters from the same structure.
67 citations
Patent•
27 Feb 1996TL;DR: In this paper, a pass control circuit (120) is coupled to the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).
Abstract: A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one embodiment, the circuit (110) comprises a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).
Book•
04 Mar 1996
TL;DR: This chapter discusses Integrated Circuit Theory including Digital Circuit Theory Including Inductance, which applies to Many-Loop Circuits, and its application to Devices And of Low-Frequency Circuits.
Abstract: Preface. 1. Definition of the Problems. Introduction--Circuit Complexity.Complexity and High Speed.Time and Frequency Metrics in Digital and in Analog Circuits.Lumped Versus Distributed Equivalent Circuits.Computational Methods of Analysis.Essential Parasitics.Estimation of Inductance Effects.Lumped Versus Distributed Reactive Components.Voltage and Current in a Circuit.Voltage Measurements.Equivalent Circuit and Distinctive Circuit Nodes.Modes and the Equivalent Circuit.Isolated Versus Nonisolated Inductances. 2. Models of Devices And of Low-Frequency Circuits. Introduction.Electron Triodes.Device Characteristics.Amplification Mechanisms.High-Frequency Circuit Model.Equivalent Circuit Model.Analysis of the Simple Digital Circuit Models.Modes of a Uniform and Straight RC Chain.Understanding the Modes of the Circuit--I.Understanding the Modes of the Circuit--II.Non-monotonic RC Circuit Response.Mechanisms of Long-Lasting Metastable States in CMOS D-Latches. 3. Ground and Voltage Sources. Introduction.Communication Between Circuits.Ground as an Isolation Wall.Impedance of a Power Supply.Power Supply Connection in Hybrid Integrated Circuits.Interconnect Response Analysis Methods.Grounds of Strongly Connected Circuit Blocks.Transients in an Input/Output Buffer Frame--I.Transients in an Output Buffer Frame--II.Response of the Output Buffer Frame Immediately after Discharge.Interpretation of I/O-Buffer-Frame Noise Simulation. 4. Digital Circuit Theory Including Inductance. Introduction.Inductance Effects.Local Time in an Oscillatory LCR Circuit.Analysis of a Device Driving an Interconnect.Generalization of the Theory to Many-Loop Circuits.Time Shift Between the Nodes.Modes of a Uniform Straight LCR Chain.Elmore's Formula for the LCR Chain Circuit. 5. Microstates, Submicrostates, And Local Times. Introduction.Forward and Backward Flow of Local Time.Microstates and Submicrostates--I.Microstates and Submicrostates--II.Microstates and Submicrostates--III.Mutual Inductance Coupling.Circuits Having No Backbone RC Circuit.Inductance and Black Boxes.Quasistatic Charge Transfer. 6. Complexity of Interconnects. Introduction.Complexity of Interconnects.Initial Conditions of RC Transmission Lines.Common-Ground RC Transmission Lines.RC Transmission Line with Ground Resistance.Coupled RC Transmission Lines.LC Transmission Line.LCR Transmission Lines.Future Directions for Integrated Circuit Theory. References. Index. 020163483XT04062001
TL;DR: In this paper, an RC oscillator exhibiting chaotic behaviour is described, which contains two opamps, a Wien bridge and a diode used as a nonlinear device, and the typical waveforms, phase portraits, the power spectra and the correlation dimension of the attractor are presented to illustrate the chaotic oscillations.
Abstract: An RC oscillator exhibiting chaotic behaviour is described. It contains two opamps, a Wien bridge and a diode used as a nonlinear device. The typical waveforms, the phase portraits, the power spectra and the correlation dimension of the attractor are presented to illustrate the chaotic oscillations.
TL;DR: The optimal clock sizing problem is formulates and a sizing optimization algorithm based on Gauss-Marquardt's least square minimization method is proposed based on a distributed RLC interconnect model which takes into the account the nonnegligible inductance in high-speed long interconnects.
Abstract: To achieve path delay balance, instead of making faster paths slower by elongating wires used in most zero skew clock routing methods, we make slower paths faster by the wire sizing. The wire sizing technique is frequently used by IC designers to minimize the clock skew caused by the unbalanced RC delays and transmission line noises. However, manual sizing takes a long time and lacks accurate relationship between the timing and wire widths. This paper formulates the optimal clock sizing problem and proposes a sizing optimization algorithm based on Gauss-Marquardt's least square minimization method. The minimum skew is achieved by this method due to its uphill mechanism of searching the global minimum by selecting a proper Lagrange multiplier dynamically at each iteration. The optimization is guided by the delay calculation based on a distributed RLC interconnect model which takes into the account the nonnegligible inductance in high-speed long interconnects (such as on the substrate of a multichip module). The algorithm and delay model can handle a general clock network including loops such as a clock mesh. For testing examples of equal path length clock trees, this algorithm can further achieve 10/spl times/ skew reduction and 14% path delay reduction after the sizing.
TL;DR: In this article, the authors presented novel oscillator circuits using the current-feedback operational amplifier (CFOA) and five passive elements, each of which enjoys independent control of the frequency and the condition of oscillation.
Abstract: Novel oscillator circuits using the current-feedback operational amplifier (CFOA) are presented. Each circuit uses one CFOA and five passive elements. Some of the circuits enjoy independent control of the frequency and the condition of oscillation. Experimental results are included.
TL;DR: In this paper, a general synthesis method is given for the realisation of an nth-order lowpass voltage transfer function, using the active RC circuit containing a minimum number of capacitors and n+1 current conveyors at most.
Abstract: A general synthesis method is given for the realisation of an nth-order lowpass voltage transfer function, using the active RC circuit containing a minimum number of capacitors and n+1 current conveyors at most. All the current conveyors are of the noninverting type, and they act as voltage followers. This makes the proposed circuit simple and attractive.
12 May 1996
TL;DR: In this paper, a novel implementation method of hysteresis chaos generator is proposed, which consists of two capacitors, two resistors, one linear VCCS (Voltage Controlled Current Source) and one hysteressesis VCCs.
Abstract: This paper proposes a novel implementation method of hysteresis chaos generator. The implementation circuit consists of two capacitors, two resistors, one linear VCCS (Voltage Controlled Current Source) and one hysteresis VCCS. These VCCSs are implemented by using OTA. Then, as a simple application example of this circuit, we propose master-slave ladder network that exhibits various spatiotemporal patterns. This application is realized by synchronization and control of chaos. These phenomena are guaranteed theoretically and confirmed by laboratory experiments.
Patent•
11 Jan 1996TL;DR: In this article, a high voltage generator circuit consisting of a boosting circuit, a limiter circuit, and a bypass circuit is described, where the output voltage exceeds the limit voltage of the limiter and an output current of the boosting circuit is bypassed and discharged by the bypass circuit.
Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.
Patent•
21 May 1996
TL;DR: In this article, a method and apparatus for producing a temperature stabilized frequency from a signal generator in a monitoring station is described, where the signal generator monitors the voltage response of an RC circuit where the resistive portion is formed by a thermistor, to produce a timedependent signal.
Abstract: A method and apparatus for producing a temperature stabilized frequency from a signal generator in a monitoring station is described. The signal generator monitors the voltage response of an RC circuit where the resistive portion is formed by a thermistor, to produce a time-dependent signal. A comparator compares the time-dependent signal to a reference voltage to determine a rise time of the voltage across the capacitor. Based upon a software timer loop, the signal generator determines a temperature range by selecting data from a look-up table based upon the rise time of the RC circuit.
TL;DR: In this article, a new mathematical model for facilitated mass transport in a polymeric membrane with a fixed-site carrier was developed by extending the single RC circuit model, which was derived by assuming concentration fluctuation and analogy between electron transport in parallel resistor-capacitor (RC) circuit and facilitated transport membrane.
Patent•
10 Oct 1996
TL;DR: In this paper, a circuit board having a load is inserted into a chassis of a digital system while the system remains in operation, and the circuit board includes a soft start circuit that allows the load to charge gracefully after the enhancement voltage is provided.
Abstract: A circuit board having a load is inserted into a chassis of a digital system while the system remains in operation. During insertion, a ground potential is provided to the circuit board. Next, one or more voltage potentials are provided, however, no electrical path is provided from the voltage potentials, through the load, to ground. An enhancement voltage is provided to the circuit board, allowing the load to charge. Finally, a backplane is connected to the circuit board after the load has charged. The circuit board includes a soft start circuit that allows the load to charge gracefully after the enhancement voltage is provided. In one embodiment, the soft start circuit includes an RC circuit connected to a switch which gradually turns on as the RC circuit charges, thereby providing an electrical path from the circuit board load to ground through the switch. The switch may be a MOSFET. Once the circuit board load is charged, connecting the backplane bypasses the MOSFET, thereby eliminating nearly all quiescent current flow through, and associated power dissipation in, the MOSFET. The circuit board is extracted from the chassis of the digital system by first disconnecting the backplane. When this occurs, the MOSFET is no longer bypassed by the backplane connection and quiescent current again flows through the MOSFET. Next, the enhancement voltage is removed, allowing the MOSFET to gradually turn off as the RC circuit discharges, thereby removing the electrical path from the load to ground. The voltage and ground potential are then removed.
Patent•
NEC1
TL;DR: In this article, an impedance matching circuit used in a transmitter circuit, an occurrence of a reflection wave in an antenna is suppressed, where the impedance of the antenna is matched with an impedance of a power amplifying circuit.
Abstract: In an impedance matching circuit used in a transmitter circuit, an occurrence of a reflection wave in an antenna is suppressed. The impedance matching circuit in a transmitter circuit includes a modulating circuit for modulating an input signal to output a modulation signal, a power amplifying circuit for power-amplifying the modulation signal, an antenna for outputting the signal power-amplified by the power amplifying circuit, a demodulating circuit for demodulating the signal power-amplified by the power amplifying circuit to output a demodulation signal, a band-outside-component detecting circuit for detecting a band-outside-component of the demodulation signal, a control circuit for outputting a control signal based upon the signal derived from the band-outside-component detecting circuit, and an impedance matching circuit for matching an input impedance of the antenna with an impedance of the power amplifying circuit by changing an impedance of the impedance matching circuit based upon the control signal.
TL;DR: In this paper, a general synthesis method for the realisation of an nth-order voltage transfer function using an active RC circuit comprising a commercially available active component, AD844, which is equivalent to the combination of a second generation current conveyor having a gain of + 1 (CCII+) and a unity gain voltage buffer.
Abstract: The author presents a general synthesis method for the realisation of an nth-order voltage transfer function using an active RC circuit comprising a commercially available active component, AD844, which is equivalent to the combination of a second generation current conveyor having a gain of +1 (CCII+) and a unity gain voltage buffer. The use of this active component simplifies the implementation, making the proposed circuit attractive.
TL;DR: In this article, the maximum input signal level that does not cause clipping and slew-rate limiting effects is investigated for current-mode active-RC filters involving second generation current conveyors (CCIIs).
Abstract: The maximum input signal level that does not cause clipping and slew-rate limiting effects is investigated for current-mode active-RC filters involving second generation current conveyors (CCIIs), and a simple formula is derived for the maximum input signal amplitude that does not cause nonlinearities.
Patent•
15 Apr 1996TL;DR: In this article, a frequency adjustable, zero temperature coefficient referencing ring oscillator circuit is presented. But the operating frequency of the ring oscillators can be adjusted after fabrication and passivation of the integrated circuit device.
Abstract: A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circuit that controls the switching circuit to establish the frequency of the output signal, the control circuit including field-effect transistors which are operated as output resistance controllable devices and which have their operating points, and thus their output resistances, established by a reference voltage that is produced by a precision reference voltage generating circuit so that the operating frequency of the ring oscillator circuit can be set by adjusting the value of the reference signals produced by the precision reference signal generating circuit and is maintained at the setpoint value because the precision reference voltage generating circuit operates independently of variations in temperature and/or the power supply voltage. The ring oscillator circuit is fabricated as an integrated circuit device and the operating frequency of the integrated circuit ring oscillator circuit can be adjusted after fabrication and passivation of the integrated circuit device.
10 Sep 1996
TL;DR: In this article, the authors present an innovative transient clamp circuit that makes use of some properties of a variable voltage clamp and varies its RC time constant depending upon whether or not the integrated circuit is mounted on a printed circuit (PC) board.
Abstract: This paper summarizes several basic supply clamping techniques and presents an innovative transient clamp circuit that makes use of some properties of a variable voltage clamp. This circuit varies its RC time constant dependent upon whether or not the integrated circuit (IC) is mounted on a printed circuit (PC) board. If the IC is mounted the time constant of the transient clamp is set very short so it will not interfere in the normal operation of the device. However, if the IC is free standing the RC time constant is set much longer to ensure the clamp will stay on long enough to discharge the entire ESD pulse should the need arise. This clamp circuit was used as a component in the electrostatic discharge (ESD) protection network for an analog intermediate frequency (IF) limiter IC. Human Body Model (HBM) ESD levels increased from less then 300 volts to greater then 2000 volts due to the addition of this protection network.
04 Jun 1996
TL;DR: In this paper, two distinct transimpedance filter topologies are described, one based on the well known multiple feedback (MFB) filters while the second resembles typical Q-enhancement configurations.
Abstract: In this paper two novel distinct transimpedance filter topologies are described. The first one is based on the well known multiple feedback (MFB) filters while the second resembles typical Q-enhancement configurations. For both classes low- and band-pass responses have been fully developed taking into consideration several parameters: frequency response, input-output impedances and noise. Q-enhancement filters have been found to be more versatile if several parameters are to be optimized, at the expense of using more amplifiers. Transimpedance filters find direct application in some sensors and D/A converters which provide current as an output signal.
Patent•
17 May 1996TL;DR: In this article, the current detection circuit includes a transistor connected between the input and the output and controlled at its gate by a reference current detector, which is connected at input to at least one column of the memory and at output to a corresponding read circuit.
Abstract: In a memory in integrated circuit form, organized as a matrix of rows and columns, a current detection circuit is connected at input to at least one column of the memory and at output to a corresponding read circuit. The current detection circuit includes a transistor connected between the input and the output and controlled at its gate by a reference current detection circuit.
01 May 1996
TL;DR: In this paper, a digital-analog integrator was developed for use with inductive magnetic sensors in long-pulse tokamaks, where continuous compensation of input offsets was accomplished by alternating analog-to-digital convertor samples from the sensor and a dummy load, while an RC network provided passive integration between samples.
Abstract: A digital-analog integrator has been developed for use with inductive magnetic sensors in long-pulse tokamaks. Continuous compensation of input offsets is accomplished by alternating analog-to-digital convertor samples from the sensor and a dummy load, while an RC network provides passive integration between samples. Typically a sampling rate of 10 kHz is used. In operational tests on the DIII-D tokamak, digital and analog integration of tokamak data show good agreement. The output drift error during a 1200 s integration interval corresponds to a few percent of the anticipated signal for poloidal field probes in International Thermonuclear Experimental Reactor (ITER), and bench tests suggest that the error can be reduced further.
Patent•
06 May 1996TL;DR: In this article, a self-testing self-test circuit with a built-in self test is defined, comprising of a circuit to be tested, a space compaction circuit coupled to the output of the test circuit, and an analysis circuit.
Abstract: A circuit with a built-in self test, comprising: a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.