Showing papers on "RC circuit published in 1997"
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TL;DR: This paper proves that the Elmore delay measure is an absolute upper bound on the actual 50% delay of an RC tree response and proves that this bound holds for input signals other than steps and that the actual delay asymptotically approaches theElmore delay as the input signal rise time increases.
Abstract: The Elmore delay is an extremely popular timing-performance metric which is used at all levels of electronic circuit design automation, particularly for resistor-capacitor (RC) tree analysis. The widespread usage of this metric is mainly attributable to it being a delay measure that is a simple analytical function of the circuit parameters. The only drawback to this delay metric is the uncertainty of its accuracy and the restriction to it being an estimate only for the step response delay. In this paper, we prove that the Elmore delay measure is an absolute upper bound on the actual 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore metric as we use it as a performance metric for design automation.
193 citations
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IBM1
TL;DR: In this article, the authors present a noise estimation metric for RC circuits, which is an upper bound for the Elmore delay in timing analysis and is especially useful for noise criticality pruning and physical design based noise avoidance techniques.
Abstract: Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.
170 citations
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TL;DR: A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner and the error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user.
Abstract: A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. The error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user. Networks are represented by admittance matrices throughout the analysis, and this representation both simplifies interfacing the reduced networks with circuit simulators and facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.
151 citations
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09 Jun 1997TL;DR: In this paper, the optimal number of repeaters to be inserted along a resistive interconnect line for reduced delay is analyzed. And the analytical model used in these design equations is based on the /spl alpha/-power law I-V equations for modeling short channel devices and exhibits a maximum error of 16% for typical RC loads as compared to SPICE.
Abstract: In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. Design equations for determining the optimum number of repeaters to be inserted along a resistive interconnect line for reduced delay are presented. Power dissipation in repeater chains is also analyzed. The analytical model used in these design equations is based on the /spl alpha/-power law I-V equations for modeling short-channel devices and exhibits a maximum error of 16% for typical RC loads as compared to SPICE.
134 citations
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08 Aug 1997TL;DR: In this paper, a tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter.
Abstract: A tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter. A decoder converts the RC product as measured by the A/D converter into a digital code which, when applied to the appropriate capacitor array, sets the array capacitance to compensate for the difference between the measured RC product and the nominal design value.
115 citations
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12 Apr 1997TL;DR: In this paper, the output frequency of the RC oscillator may be adjusted by selecting different values of the low voltage level (V1), so that the oscillator signal does not exceed the precise high and low voltage levels (V2, V1).
Abstract: An RC oscillator circuit (10) within a microcontroller chip includes first and second comparators (16, 18) having their outputs respectively coupled to set and reset inputs of a flip-flop (20) whose output is coupled to a series RC network (22, 14) for controlling charging and discharging of a capacitor (14) of the RC network between precise high and low voltage levels (V2 and V1). One input of each comparator is coupled to the RC network, while the second input is coupled to a respective modified high and low threshold voltage level (Vh', V1'), so that the oscillator signal does not exceed the precise high and low voltage levels (V2, V1). The output frequency of the oscillator may be adjusted by selecting different values of the low voltage level (V1).
99 citations
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10 Jun 1997TL;DR: In this article, a new computationally efficient and accurate model for ferroelectric capacitors is presented, which uses a unique algorithm to account for the history dependence of the capacitors, and the charge-voltage relationship, Q(v) is described by a set of analytical functions with few parameters that can be easily extracted from electrical measurements of test capacitors.
Abstract: A new computationally efficient and accurate model for ferroelectric capacitors is presented. This model uses a unique algorithm to account for the history dependence of ferroelectric capacitors, and the charge-voltage relationship, Q(v is described by a set of analytical functions with few parameters that can be easily extracted from electrical measurements of test capacitors. This model has been successfully implemented into SABER. Comparisons of simulation results with measurements show an outstanding predictive ability for arbitra voltage inputs. INTRODUCTI~N The growing interests in using ferroelectric materials in integrated circuits, especially in memory applications require accurate models for ferroelectric capacitors for circuit simulation and optimization. However, the Q-V (or C-v) relationships of ferroelectric capacitors are nonlinear and have nonlocal memories [1,2], i.e., the state of a capacitor is not uniquely determined by its present position on the Q-V plane, but also depends on voltage experienced at previous times. Most of the previous circuit models either do not [3,4] or incorrectly account for the history dependence [ 5 ] . Others require detailed information of microscopic material structure and complicated numerical analysis which is difficult to implement into a circuit simulator [6]. In this work, we found that the complex behavior of a ferroelectric capacitor is similar to that of Preisach hysteresis, widely used in the area of ferromagnetics [ 2 ] . We present a computationally efficient model that incorporates all of the major properties of Preisach hysteresis and correctly accounts for the history dependence of ferroelectric capacitor. For simplicity, time dependent effects such as polarization relaxation are neglected. THE MODEL A Preisach hysteresis is a macroscopic system that can be represented as a superposition of simple hysteresis units, and each unit has a rectangular hysteresis loop [2]. In the case of a ferroelectric thin film capacitor, it can be represented as a system of parallelly connected, non-interacting units as shown in Fig. 1. The switching charge 0, and the coercive voltages a and , B for each unit can be different, Let p(a ,B) describe the coercive voltage distribution, and D,p is the direction operator such that DCpV(t) = 1(-1) if the unit with coercive voltages (a,p) is switched to the positive (negative) polarity at time t . The total charge can then be written as Q ( t ) = Aa>P)fiapJ’(t)da@‘ (1) The Preisach type model can be numerically implemented by using Eq. 1. Although this approach is straightforward, it requires the numerical evaluation of double integrals in Eq. 1, which is a time-consuming procedure. In addition, the determination of the coercive voltage distribution p(a,,B) requires differentiations of experimentally obtained data. These differentiations may strongly amplify errors or noise inherently present in any experimental data. In this work, we present a method that incorporates the special properties of Preisach hysteresis while completely circumventing the above difficulties. Detailed studies of the Preisach type models and rigorous proofs of these properties can be found in [2]. For clarity, the linear contribution to the net charge is omitted in the discussion below. It can be easily included later by adding a linear capacitor C1 in parallel with the ferroelectric component. A. Saturation curve -An important property of Preisach hysteresis and ferroelectric hysteresis is the well defined saturation loop. Regardless of the previous history of the capacitor, the QV point must always lie on or within the saturation loop; and the magnitude of dQ/dV at any given Q-V point must be no greater than that of the saturation curve (of the same direction) at the same V. Let F f ( V ) and F & ( V ) denote the ascending and descending branch of the saturation loop respectively. They can take any functional form as long as they fit the experimental loop. The hyperbolic tangent is chosen here because it is simple, has the correct physical properties, and provides reasonable fit for most ferroelectric thin film capacitors, i.e., where Qs is the maximum charge contribution from ferroelectric switching, Vc+, (Vc) is the covercive voltage for the ascending curve (descending curve), and the parameter a describes how fast the hyperbolic tangent approaches ?Q,s (see Fig. 2). B. Memory Formation -Previous history of the capacitor is “remembered” by keeping track of the previous turning points on the Q-V plane. A turning point is where the Q-V curve changes direction or where dV/dt changes sign (see Fig. 3). The +(-) sign is used to distinguish the points where V ( t ) is a local maxima (minima). Although Preisach hysteresis has nonlocal memories, not all of its prior history needs to be “remembered”. For example, since the saturation loop is well defined, if a large voltage is applied across the capacitor such that its Q-V point is on the saturation curve, its behavior in the future no longer depends on its past history. To be more specific, only the alternating series of dominant input voltage extrema are important (see Fig. 4). Table 1 shows some examples of how the turning points in the memory are continuously being wiped out and updated. Because of this memory wiping-out property, the number of points that need to be stored generally does not grow continuously with time. By default, the end points of the saturated loop (m,QLy) and (-m,-Q&), denoted by S and -S respectively, are always the first two turning points stored in memory and are never wiped out. C. Inside the Saturation Loop -Once the Q-V point is inside the saturation loop, as the voltage is jncreased(decreased), the QV curve always passes through previous +(-) turning points stored in memory (see Fig. 5 ) . The Q-V curve connecting any two adjacent turning points ( v i , q , ) and ( ~ ~ + ~ , q ; + ~ ) , denoted by f i ? ( V ) or f, J ( V ) is given by where m, and b, are coefficients that need to be determined for each pair of turning points such that qi = m, F $ (v, ) + b, and q,+1 = mjF 2 (v,+l) + b, hold. It can be shown that F 1 (VI = Qs tanh[a(V V,, I] (2) f, $ ( V ) = m i F $ ( V + b / (3) 4; -q i+l F 1 (v, F 1 (vi+, m, = is always between 0 and 1. This means df, 1 idV I dF $ idV , or the magnitude of dQ/dV at any point inside the saturation loop is always a fraction of that of the saturation loop at the same V. SIMULATION RESULTS AND DISCUSSION Model simulations are compared with experimental data for 2000A SrBi,Ta,O, thin film capacitors experiencing complicated input voltage sequences (Figs. 6-8). The model parameters QS, Vc.+ , Vr-, U, and C/ are obtained from experimental measurements of the saturation loop. Unless otherwise specified, the model assumes the initial Q-V point to be on the saturation loop so that the only turning points in memory at the beginning are S and -S. For all cases, this model correctly describes the history dependence and memory formation of SBT capacitors. The predicted QV curves closely match the experimental data. 141 4-93081 3-75-1 /97 1997 Symposium on VLSl Technology Digest of Technical Papers REFERENCES Electrode I [ I ] B. Jiang, et al., Integrated Fenoelect., 1997, in press. [2] 1. 11. Mayergoyz, Mathematical Models of Hysteresis, Springer-Verlag New York, 1991. V [3] A. K. Kulkarni, et al., Ferroelect., 116 (1-2), p.95, 1991. Electrode 2 [4] D. E. Dunn, IEEE Trans. on Ultrasonics, Ferroelectrics, [5] S. L. Miller, et al., J. Appl. Phys. 70 ( 5 ) , p.2849, 1991. ,61 p, Zurcher, et Feroelect,, C and Frequency Control,41 (3), p.3, 1994. (4 p.205, 1995. Figure 1. (a) Preisach model applied to ferroelectric thin film capacitors. (b) The Q-V curve of eaLch unit has to lie on a rectangular loop. As the voltage is increased the ascending branch Figutt 2. The saturation curves, including only the contribution from ferroelectric dipole switchiing are described by Eq. 2. abcde is followed; as the voltage is decreased, the descending branch edfba is traced. The loop does not have to be symmetric with respect to OV. The total charge is the sum over all units. Figure 3. 0-V cuwe turning points. The extrema are stored in memory. All other input extrema example shows a capacitor %rting on the are wiped out. For the particular pulse train shown, at _ , _ % saturation loop and passing through a, b, C, d. time To, the voltage extrema stored in memory are turnin:! points a, 6, c, d. After reaching d, as the volt@e is decreased) the Qcurve passes through again? then a, and The Table 1. Examples illustrating the memory wipingout property. The voltage extrema experienced by -' . The Q-' the ferroelectric capacitor in time are listed from top to bottom. The voltages stored in the model are erased in pairs. Each new local maxima erases the previous local maxima of equal or lesser value and its following local minima: each new local minima erases the urevious local minima ofeaual or greater cay and a-S are given by Eq. 3. are determined m i and ' i in Eq, 5 4 3 2 1 0 1 2 3 4 5 Voltage (V) Figure 6 Comparison between (d) measurement and (t,) model prediction when applied pulse sequency IS SV, -5V, ( 0 SV, -0 SV)xn, -5V, and 5V The Q-Vcurve traces a, b, (c, dxn, 6, a value and i t s following lo& maxima. The entries 2 0 1 I I I I I I I I I that erased previous memories are shown in &Id. 201 1 1 1 1 1 1 1 1 1 I
98 citations
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IBM1
TL;DR: In this paper, the authors present an upper bound for coupled noise in on-chip interconnects, being similar in spirit to the Elmore delay in timing analysis, which is especially useful for noise criticality pruning and physical design based noise avoidance techniques.
Abstract: Noise analysis and avoidance is an increasingly critical step in deep submicron design Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques
94 citations
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13 Oct 1997TL;DR: In this paper, a method for designing and fabricating an integrated circuit is disclosed, where signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit.
Abstract: A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined. Post processor 520 determines if electromigration parameters are violated based on the current profile determined for each net. Widths for various segments of signal lines in the various nets are selected to be greater than or equal to a minimum width determined by post processor 520.
83 citations
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21 Feb 1997
TL;DR: In this paper, a comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of a circuit by collecting values of electrical characteristic parameters to provide a technology profile for fabrication process.
Abstract: A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of an integrated circuit. The method includes collecting values of electrical characteristic parameters to provide a technology profile for a particular fabrication process. An Interconnect Primitive Library builder provides a collection of interconnect `primitives` that any interconnect structure fabricated under the fabrication process can be broken down into, and combines it with the technology profile for simulations in a 3-dimensional field solver to extract parameterized coupling capacitances and other characteristic impedances for each interconnect primitive. An extraction tool traces a signal path of an integrated circuit and decomposes the interconnect structures on the signal path into interconnect primitives and maps them to the Interconnect Primitive Library. An RC network module provides an RC network based on the characterized parametric values in the mapped interconnect primitives. The RC network thus provided can be used to accurately estimate signal delays in a circuit simulator or delay calculator.
70 citations
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23 Oct 1997TL;DR: In this paper, a stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power is presented, where signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit.
Abstract: A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
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NEC1
TL;DR: In this article, an overvoltage protection circuit detects overvoltages in an output AC voltage from a piezoelectric transformer and switches the frequency control circuit to a provisional frequency sweeping range.
Abstract: In a drive circuit for a piezoelectric transformer that comprises an inverter circuit for supplying first and second primary electrodes of a piezoelectric transformer with a main drive voltage, a frequency control circuit having a normal frequency sweeping range, and a drive voltage control circuit for controlling input power of an input DC voltage supplied to the inverter circuit, an overvoltage protection circuit detects overvoltage in an output AC voltage from the piezoelectric transformer. On detection of the overvoltage in the output AC voltage, the overvoltage protection circuit supplies the frequency control circuit with an additional reset signal and a switching signal, thereby making the frequency control circuit switch the normal frequency sweeping range to a provisional frequency sweeping range included in the normal frequency sweeping range. The switching signal may be supplied to the drive voltage control circuit to make the drive voltage control circuit decrease the input power of the input DC voltage.
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11 Jul 1997
TL;DR: In this article, a closed-loop feedback circuit was used to enable a soft-start switch with current limiting, where the op-amp can be triggered to gradually rise from a value close to zero to some reference voltage so as to soft start a load.
Abstract: A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting The transconductance of the MOSFET is employed so that no sense resistor is required The MOSFET and op-amp are configured as a closed-loop feedback circuit in which the output of the op-amp is coupled to the gate of the MOSFET and the inverting input of the op-amp is coupled to the output of the soft-start switch via a voltage divider A first RC circuit provides a voltage to the non-inverting input of the op-amp which can be triggered to gradually rise from a value close to zero to some reference voltage so as to soft-start a load Current limiting means are effectuated by a comparator circuit and voltage dividers with capacitors The current limiting means brings the MOSFET to an OFF state and the non-inverting input of the op-amp close to zero volts if the op-amp charges a second RC circuit so that the voltage drop across its capacitor exceeds a pre-determined limit-reference, and also, once the current limiting means brings the MOSFET to the OFF state, the current limiting means allows the soft-start switch to begin a soft-start power-up after a pre-determined time dependent upon the time constant of the second RC circuit
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03 Jun 1997TL;DR: In this article, an inexpensive probe apparatus operating at high precision that can be used for both low-frequency and high-frequency measurements is presented. But it is not suitable for high frequency measurements.
Abstract: This invention is an inexpensive probe apparatus operating at high precision that can be used for both low-frequency and high-frequency measurements. A line with a first and second conductor is extended from a probe connected to a circuit component. A low-frequency or high-frequency device is alternately connected to the line. A third common conductor runs parallel to the aforementioned line and a resistor and capacitor is connected between the probe end of the aforementioned second conductor and the aforementioned common conductor.
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19 Dec 1997
TL;DR: A discharge control circuit for a power supply switching converter that, in response to a cessation of current from an AC power source, makes conductive a main switching element of the switching converter to discharge the bulk filter capacitor through the main switch element to a charge level that meets safety standards is described in this article.
Abstract: A discharge control circuit for a power supply switching converter that, in response to a cessation of current from an AC power source, makes conductive a main switching element of the switching converter to discharge the bulk filter capacitor through the main switching element to a charge level that meets safety standards. The discharge control unit includes a current limiting circuit for limiting the discharge current through the main switching element in which the rate of rise of the discharge current is controlled with the use of an RC circuit. The discharge control unit also includes a state machine that activates the current limiting circuit in response to a cessation of the modulation mode of the switching converter. The discharge control circuit also includes a reset circuit for placing the state machine in a known state during the startup of the switching converter.
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IBM1
TL;DR: In this paper, a data recording disk drive uses a circuit responsive to the removal of power to the spindle motor to generate a two-stage torque to retract the actuator and move it to a parking ramp.
Abstract: A data recording disk drive uses a circuit responsive to the removal of power to the spindle motor to generate a two-stage torque to retract the actuator and move it to a parking ramp. The spindle motor power removal circuit sends an initial signal to a first switch connected to a full-wave rectifier retract circuit and, after a predetermined delay time, a second signal to a second switch also connected to the rectifier circuit. Activation of the first switch causes only a portion of the available current from the spindle motor windings to reach the actuator, so that the actuator is moved with an initial low-level torque which is sufficient to bring the actuator to the disk OD of the disk under all circumstances. Activation of the second switch a predetermined delay time later allows all available current to reach the actuator so the actuator is then moved with a high-level torque which is sufficient to properly park the sliders on the load/unload ramp under all conditions. The spindle motor power removal circuit includes a resistor-capacitor (RC) circuit to generate the second signal. Selection of the desired delay time is made by design of the appropriate RC time constant of the RC circuit.
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13 Nov 1997TL;DR: The dominant time constant is used as a measure of signal propagation delay in an RC circuit, instead of Elmore delay, so that sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently-developed efficient interior-point methods for semidefinite programming.
Abstract: Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to high-performance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interior-point methods for semidefinite programming. The method is applied to two important sizing problems --- sizing of clock meshes, and sizing of buses in the presence of crosstalk.
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03 Jun 1997TL;DR: In this article, a sensor circuit with differential inputs Vi, Vo is used to reduce the rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo.
Abstract: The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo˜Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.
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17 Mar 1997TL;DR: Oscillation-based test strategy is applied to test active RC filters and it can be shown that some of the derived structures are achieved by simple circuit modification while for the more general case additional feedback loop network is required.
Abstract: Summary form only given. We apply the oscillation-based test strategy to test active RC filters. We develop general guidelines for the design of the oscillation-based test structures and describe in more details the resonator active filler (biquad filter) configuration. It can be shown that some of the derived structures are achieved by simple circuit modification while for the more general case additional feedback loop network is required.
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09 Jun 1997TL;DR: In this paper, the authors present a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems, which is based on the assumption that full voltage is being supplied to each of the blocks.
Abstract: The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.
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10 Nov 1997TL;DR: In this paper, a phase comparator is used to make a comparison between an internal clock signal and a clock signal supplied from an external terminal, and a charge pump circuit is provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher.
Abstract: A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.
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TL;DR: In this paper, a digital-analog integrator was developed for use with inductive magnetic sensors in long-pulse tokamaks, where continuous compensation of input offsets was accomplished by alternating analog-to-digital convertor samples from the sensor and a dummy load, while a RC network provided passive integration between samples.
Abstract: A digital–analog integrator has been developed for use with inductive magnetic sensors in long-pulse tokamaks. Continuous compensation of input offsets is accomplished by alternating analog-to-digital convertor samples from the sensor and a dummy load, while a RC network provides passive integration between samples. Typically a sampling rate of 10 kHz is used. In operational tests on the DIII-D tokamak, digital and analog integration of tokamak data show good agreement. The output drift error during a 1200 s integration interval corresponds to a few percent of the anticipated signal for poloidal field probes in International Thermonuclear Experimental Reactor, and bench tests suggest that the error can be reduced further.
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19 Dec 1997TL;DR: In this article, an analog phase-locked loop circuit (10) is used to compare the phase of a reference signal (28) to the output (12) of a phase detector circuit, a charge pump circuit (18), a regulator circuit (22), and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).
Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).
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Rohm1
TL;DR: In this article, the authors proposed a push-pull control circuit consisting of a constant-current-on type transistor Tr1 and a differential-pulse-on-type transistor Tr2 and the output voltage is Vcc(Tn+Tf)/Tf.
Abstract: This circuit improves power efficiency and reduces number of parts required in a voltage step-up circuit. This circuit includes a switching control circuit and a voltage transformer circuit. The control circuit is a push-pull circuit comprising a constant-current-on type transistor Tr1 and a differential-pulse-on type transistor Tr2. The transformer circuit comprises an NPN type switching transistor Tr3, a coil L1, a diode D1, and a electrolytic capacitor C2. With Tn being the duration of the ON state of Tr3, and Tf the duration of the OFF state, the output voltage is Vcc(Tn+Tf)/Tf. Since the constant-current-on type transistor Tr1 is laid closer to the power source than the differential-pulse-on type transistor Tr2, the switching transistor Tr3 can be driven directly and no PNP type transistor is necessary.
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26 Jun 1997TL;DR: In this article, a circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed, which can be constructed in modular form and may include a module capable of creating a stabilized RC time constant that is likewise unchanged by variations in temperature or processing.
Abstract: A circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed. The stabilization circuit is formed to generate a reference current that is proportional to a reference capacitance C S and the thermal voltage V T . The reference current is ultimately mirrored (as the bias current) into the bipolar devices which determine the gm within the analog circuit. Since the transconductance gm of a bipolar device can be expressed as collector current, I C , divided by V T , the thermal voltage factor of the bias current itself will "cancel" the thermal voltage factor present in the transconductance. The effects related to the remaining variable, the capacitance, will be eliminated as long as the reference capacitance is formed to "track" the analog circuit capacitance by using similar types of capacitance to implement both capacitors and forming both the stabilization circuit and the analog circuit on the same silicon chip. The stabilization circuit can be constructed in modular form and may include a module capable of creating a stabilized RC time constant that is likewise unchanged by variations in temperature or processing.
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23 Dec 1997TL;DR: A high-voltage generating circuit (1) includes a highvoltage production circuit (2), a high voltage detecting circuit (3), and a control circuit (4) as discussed by the authors.
Abstract: A high-voltage generating circuit (1) includes a
high-voltage production circuit (28), a high-voltage
detecting circuit (29) and a control circuit (30). The
high-voltage production circuit (28) includes clamping
diodes (6, 7) to provide a good response for stabilizing a
high voltage. The control circuit (30) applies pulse-width
control to a power source voltage (8). The high-voltage
detecting circuit (29) has a high-voltage circuit section
(29a) to which a voltage of 1 kV to several tens of
kilovolts is applied and a low-voltage circuit section (29b)
to which a voltage of several tens of volts is applied. The
high-voltage circuit section (29a) comprises a parallel
circuit including voltage-dividing resistors (9, 10, 11, 12)
and a speed-up capacitor (14). The speed-up capacitor (14)
is set to 1000 pF or less.
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02 Nov 1997TL;DR: In this article, a short-channel transistor model is used as a foundation for the development of delay and power expressions to develop a design methodology for inserting repeaters into an RC tree network.
Abstract: In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The proper insertion of repeaters alleviates the quadratic increase in propagation delay with the interconnect length while decreasing the power dissipation by reducing the short-circuit current. These repeaters are inserted within different types of common resistive interconnect structures, such as a line or a tree. The application of repeaters to RC tree structures is discussed. A tree topology is a common interconnect structure frequently found in VLSI circuits. A short-channel transistor model is used as a foundation for the development of delay and power expressions to develop a design methodology for inserting repeaters into an RC tree network. Power dissipation expressions for these repeater structures are presented which consider both dynamic and short-circuit power. These design expressions are validated against simulated experiments with a maximum 11% and 16% deviation from SPICE for delay and power, respectively.
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09 Jun 1997TL;DR: The sensitivity of log-domain integrators to DC biasing offsets is discussed and a transistor-level all-NPN differential log- domain integrator is proposed and used to implement a fully tunable balanced 600 MHz biquad.
Abstract: General transfer characteristics of log-domain integrators necessary to realize different log-domain filter topologies, based on LC ladder synthesis, are described. As an example, a transistor-level all-NPN differential log-domain integrator is proposed and used to implement a fully tunable balanced 600 MHz biquad. The integrator is then used to implement 4/sup th/ and 6/sup th/-order balanced bandpass filters. The sensitivity of log-domain integrators to DC biasing offsets is discussed. These offsets are minimized using a BiCMOS common mode feedback circuit. Simulation results are presented with an emphasis on distortion analysis.
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09 Jun 1997TL;DR: The use of the MOSFET as a capacitor, a linearized resistor, a distributed RC filter element, as a passive voltage amplifier, and as a discrete-time parametric amplifier is discussed in this paper.
Abstract: This paper discusses uses of the MOSFET other than as a transconductor or switch. Several possibilities are reviewed, and new ones are described. The techniques discussed include the use of the MOSFET as a capacitor, as a linearized resistor, as a tunable distributed RC filter element, as a passive voltage amplifier, and as a discrete-time parametric amplifier; also described are resistive-gate MOSFETs and resistive gate/resistive body MOSFETs.
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26 Aug 1997TL;DR: In this article, a waveform shaping circuit for use in a function circuit is provided which minimizes interference with a feedback circuit of the function circuit and a load, including a voltage transfer unit and a voltage-to-current converter unit.
Abstract: A waveform shaping circuit for use in a function circuit is provided which minimizes interference with a feedback circuit of the function circuit and a load. The waveform shaping circuit disposed in the function circuit includes a voltage transfer unit and a voltage-to-current converter unit. The voltage transfer unit transfers a voltage at an output terminal of an operational amplifier to the converter unit in an electrically isolated condition. The converter unit has a predetermined threshold for the magnitude of the voltage at the output terminal. The converter unit supplies an inverting input terminal of the operational amplifier with a current having a magnitude depending on a relationship in magnitude between the voltage at the output terminal and the predetermined threshold. In one embodiment of the invention the waveform shaping circuit is used to prevent the onset of instability in a high order delta sigma modulator.