Showing papers on "RC circuit published in 1999"

TICER: realizable reduction of extracted RC circuits

Abstract: Time Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (/spl sim/10/sup 7/ nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.

Parallel RC current detection circuit and DC/DC converter with a parallel RC current detection circuit

Abstract: An RC series circuit is provided in parallel with an inductor. The RC series circuit is comprised of a resistor and a capacitor which are connected with each other in series. A voltage across the capacitor is applied to a detection circuit. The detection circuit detects inductor current flowing through the inductor based on the applied voltage. If the inductance of the inductor, the parasitic resistance value of the inductor, the capacitance of the capacitor and the resistance value of the resistor are L, RL, C a and R a , respectively, the RC series circuit is designed so as to satisfy L/RL=C a *R a .

Input-circuit, output-circuit, input-output circuit and method of processing input signals

Abstract: An input-output circuit in which, even if variations in logic threshold voltages occurs, a logic signal can be exactly recognized on the basis of small-amplitude signals supplied. The input-output circuit of the present invention contains a threshold value detecting circuit(15), an amplifying section (14) used to output a voltage having amplitude center level of a small-amplitude signal, to amplify the small-amplitude signal to a predetermined amplitude level, to convert the small-amplitude signal to a logic signal (rectangular wave) that can be processed by a CMOS internal circuit (16)and to feed the converted signal through an output terminal to the CMOS internal circuit (16), a constant current circuit (13) used to change amplification factor of the small-amplitude signal inputted, and a feedback amplifier (A2) to compare the amplitude center voltage of the small-amplitude signal with a voltage supplied from the threshold value detecting circuit (15) and to feedback a voltage to the constant current circuit (13) so that the amplitude center voltage of the signal amplified by the amplifying section (14) is equal to a voltage set by the threshold value detecting circuit (15).

Exact curvature-correcting method for bandgap circuits

Abstract: A curvature corrected bandgap reference voltage circuit, the output voltage of which is substantially linear and independent of the operating temperature of the circuit. The circuit includes a voltage divider network comprised of a first resistor and a second resistor connected in series. A first compensating circuit provides a first, linear, operating temperature-dependent current, and a second compensating circuit provides a second, logarithmic, operating temperature-dependent current. The first current is supplied to the first resistor of said voltage divider network, while the second current is supplied to the second resistor of the voltage divider network.

Apparatus and method for detecting electrical resistance change in connectors to a remote mounted sensor

Abstract: A control system detects an electrical resistance change in a connector coupling a remote mounted temperature sensor to a control system. A control system determines the resistance of the sensor or the connector by selectively charging or discharging a capacitor through a unidirectional circuit element or the sensor. The control system is disclosed as controlling a water heater system, although such control systems may be used to control other systems using remote mounted sensors. A calibrating circuit is used to measure a transient response of an RC circuit, from which resistance can be derived.

Frequency-dependent crosstalk simulation for on-chip interconnections

Abstract: An extensive study of crosstalk simulation issues for on-chip interconnections was performed for representative six-layer Al(Cu) structures. Guidelines are given for the range of conditions when R(f)L(f)C versus RLC versus RC circuit representations are valid. Examples are also given of realistic short and long coupled-section interactions and the effect of in-plane neighboring connections is discussed. A frequency-dependent crosstalk simulation technique is shown. All simulation results are verified through measurement of a comprehensive set of experiments built with a large range of line widths and spaces on various layers with both in-plane and vertical coupling. Signal propagation and crosstalk are analyzed over the temperature range -160/spl deg/C to +100/spl deg/C and interconnect bandwidth limitations predictions are given.

Adaptive body biasing circuit and method

Abstract: An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.

Low-sensitivity, low-power active-RC allpole filters using impedance tapering

Abstract: A procedure for the design of allpole filters with low sensitivity to component tolerance is presented. The filters are based on resistance-capacitance (RC) ladder structures combined with single operational amplifiers. It is shown that by the use of impedance tapering, in which L-sections of the RC ladder are successively impedance-scaled upwards, from the driving source to the amplifier input, the sensitivity of the filter characteristics to component tolerances can be significantly decreased. Impedance tapering is achieved by the appropriate choice of component values. The design procedure, therefore, adds nothing to the cost of conventional circuits; component count and topology remain unchanged, whereas the component values selected for impedance tapering account for the considerable decrease in tolerance sensitivity.

A compact network for eliminating parametric oscillations in high power MMIC amplifiers

Abstract: High power pHEMT (and HBT) power amplifiers frequently have oscillations that occur only when the amplifier is driven near compression; under small signal conditions, oscillations are not present. We have developed a compact RC network that effectively eliminates drive dependent subharmonic and spurious oscillations in pHEMT power amplifiers. The circuit is very compact and can be incorporated in existing MMIC power amplifier designs with little or no additional tuning to the circuit.

Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices

Abstract: This paper presents a comprehensive 2-D and 1-D study of the self-heating effect in thin Silicon-on-Insulator (SOI) and Partial SOI LDMOS power devices. A simple 1-D self-heating model based on a PSPICE RC thermal circuit which accounts for the temperature rise in on-state, transient and short-circuit conditions is developed. Unlike previous 1-D modelling attempts for SOI devices, our model takes into account the feedback effect of the local device temperature on the thermal conductivity and specific heat through an equivalent electrical RC network consisting of voltage controlled resistors and capacitors. The 1-D model is thoroughly assessed against extensive 2-D thermal simulations performed using the SILVACO-ATLAS device simulator and the results indicate an excellent agreement in all operating conditions. Furthermore, an accurate comparison between the thin SOI and Partial SOI devices is carried out.

‘R-lens filter’: An (RC)n current-mode lowpass filter

Abstract: A continuous-time (RC)/sup n/ lowpass filter is presented that can be fully integrated with cutoff frequency down to the 0.1 MHz range. The circuit is based on a cascade of new compact RC-cells that provides current amplification and filtering with minimum power dissipation (<15 /spl mu/W/pole) using a single supply voltage (2 V). The high value resistance of the RC-cell is obtained by means of a current conveyor feedback that de-magnifies the signal current flowing in a small physical resistor. The circuit is intrinsically low-noise due to a 'cooling effect' in the equivalent resistor.

Current conveyor chaos generators

Abstract: New RC chaos generators that utilize the second-generation current conveyor (CCII) as the active building block are presented. The very small input resistance associated with the current conveyor low-impedance input terminal is shown to be responsible for stimulating the circuits' chaotic nature. The proposed chaotic oscillators originate from two sinusoidal oscillator circuits which are modified for chaos by replacing one of the linear resistors with a nonlinear resistor of antisymmetric current-voltage characteristics and adding a single capacitor. The elementary linear design equations of the sinusoidal oscillators are used as a start point for chaos modification to estimate all component values and identify tunable elements. Mathematical models of the proposed generators are derived and further modified to demonstrate chaotic behavior with odd symmetrical nonlinearities. Suitability for VLSI integration is discussed. PSpice circuit simulations, numerical simulations of the derived models, and experimental results are included.

Optical semiconductor diode driver circuit and optical tranceiver module

Abstract: An optical semiconductor diode driver circuit, which is stably operable even with the supply of a source voltage slightly higher than the forward operation voltage of an optical semiconductor diode to be driven and can output switch current and voltage sufficient for driving the optical semiconductor diode, includes a pre-driver circuit operating as a limiting amplifier, and an output circuit responsive to a pulse-shaped voltage output from the pre-driver circuit and outputting a drive pulse current to the optical semiconductor diode as an external load. The output circuit is basically a type of the emitter-coupled amplifier which has either a differential configuration or a similar one to a Schmitt circuit and whose common-emitter loads are composed of a resistor and a variable constant current source to determine a amplitude of the output current pulse with small rise and fall times. Since a variable constant current source is added, the circuit alleviates influences from variations of the impedance of the load and the operating environment without any degradation of high frequency characteristics.

Apparatus for I/O leakage self-test in an integrated circuit

Abstract: According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O circuit. In a test mode of operation, the leakage detection circuit tests the first I/O circuit for excessive leakage current. According to another embodiment, the integrated circuit also includes a first resistor coupled between a line voltage and the first I/O circuit and a second resistor coupled between the first I/O circuit and ground. Further, the integrated circuit includes a second I/O circuit coupled to the leakage detection circuit and the first and second resistors. The leakage circuit also tests the second I/O circuit for excessive leakage current in the test mode of operation.

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

Abstract: The dynamic and short-circuit power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving an inductance-capacitance (LC) transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed-form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. A closed form solution for the short-circuit power is also presented. These solutions agree with circuit simulations within 11% error for a wide range of transistor widths and line impedances for a 0.25-/spl mu/m CMOS technology. The ratio of the short circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects becomes more significant as compared to a resistance-capacitance (RC)-dominated interconnect line.

Realizable reduction for RC interconnect circuits

Abstract: Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtaining realizable and accurate reduced models for two-port and multi-port RC circuits. The proposed method is also particularly suitable for interconnect reduction for nonlinear circuit simulation and for interconnect post-processing in a parasitic extractor. The method has two limitations. First, it only considers the first few moments of the transfer function; however, that is accurate enough for RC circuits. Second, the amount of interconnect reduction is topology dependent. Although, most on-chip interconnect topologies are well suited for the method proposed. Accuracy and efficiency of the proposed method is demonstrated for various realistic examples.

Hotswappable chassis and electronic circuit cards

Abstract: A system for controlling power application to an electronic component during a hotswap operation. A chassis contains a plurality of slots for interfacing with electronic components, each slot having an associated timing device. The electronic component contains a delay mechanism, such that when the electronic component interfaces with a slot in the chassis, the delay and timing mechanisms interact to create a slot timing circuit. The slot timing circuit interfaces to a ramp-up switching circuitry to produce a controlled application of power to remaining circuitry of the electronic component. The timing mechanism may be a resistor and the delay mechanism may be a capacitor, such that an RC circuit is formed which controls, in a time delayed fashion, a switching mechanism which in turn controls ramp-up of power application to the electronic component. Furthermore, each timing mechanism of each slot in the chassis may have a different timing value, such that power application to multiple electronic components, inserted simultaneously into the chassis, may have power applied in a staggered fashion, to prevent inrush and surge currents to the power supply. Still further, each switching mechanism of an electronic component may have an associated power control circuit, which when activated by the slot timing circuit, controls ramp-up of power application to remaining circuitry of the electronic component in a controlled fashion.

Method and apparatus for realizable interconnect reduction for on-chip RC circuits

Abstract: Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.

Accurate adjustable current overshoot circuit

Abstract: A write driver controls current path for current of an H-bridge circuit. The H-bridge circuit is controlled by a differential pair switch for adjusting a voltage between the differential pair switch between a first voltage when the H-bridge circuit is switched and a second voltage after the H-bridge circuit is switched.

High speed frequency divider circuit

Abstract: A high frequency divider circuit for producing output signals of half the frequency of an input clock signal includes two identical circuit sections, each producing an output signal and its complement. The circuit sections are connected to each other so that the output signals of one circuit section serve as input signals to the other circuit section. Each circuit section contains a load transistor which is controlled by one of the clock signal and the clock signal complement, and a switch transistor which is controlled by the other of the clock signal and the clock signal complement. The inventive circuit exhibits a reduced RC time constant for each circuit section and an increased output signal swing between the output signals and their respective complements, as contrasted with prior art frequency dividers, thereby increasing the overall circuit response time and its ability to operate at high frequencies.

Actively-driven thin-oxide MOS transistor shunt for ESD protection of multiple independent supply busses in a mixed-signal chip

Abstract: An electro-static-discharge (ESD) protection circuit protects internal power supplies in a mixed-signal IC. An active protection circuit is used. The ESD-protection circuit uses standard transistors and is actively enabled and disabled by standard transistors. A standard thin-oxide NMOS transistor is the ESD switch (shunt) between power supply busses. This thin-oxide transistor ESD switch is actively enabled and disabled by a control circuit. NMOS transistors in the control circuit discharge the gate node of the ESD switch when the power supplies are powered up, thus actively disabling the ESD protection circuit. When an ESD pulse is applied to a supply when powered down, a capacitor couples the rapid voltage rise to the gate node. The rising voltage turns on the ESD switch, shunting the ESD pulse to the other supply. A resistor and a p-channel MOS transistor in series then discharge the gate node to the other supply. The capacitor, resistor, and p-channel transistor form an RC network. A second RC network is connected to the other supply so that symmetric protection is provided. Slow and unresponsive thick-oxide transistors and diodes are avoided.

Method and circuit configuration for voltage supply in electric function units

Abstract: A circuit configuration and a method for supplying voltages to an electrically functional unit that has a central voltage source UC and a plurality of circuit elements. Between the central voltage source and the circuit elements, a device assigned to the circuit elements is connected. The device converts the supply voltage, delivered from the central voltage source for the respective circuit elements into a voltage individualized for the circuit elements, and optionally for the circuit element state, and delivers the converted voltage to the circuit elements.

Earth leakage protective relay

Abstract: An earth fault detection circuit employs a differential current transformer and burden resistor to sample circuit current for potential earth fault current. A second order low pass filter circuit is employed to filter out harmonics within the protected circuit and a time delay circuit is used to insure the occurrence of a true earth fault leakage condition. A circuit with an operational amplifier is used to create a symmetric power supply for the rest of the circuits from a full wave rectified AC source.

Foundations of Electric Circuits

Abstract: 1. Basic Circuit Theory. Introduction to Electrical Engineering. Physical Basis of Circuit Theory. Current and Kirchhoff's Current Law. Voltage and Kirchhoff's Voltage Law. Energy Flow in Electric Circuits. Resistances and Sources. Series and Parallel Resistances. Voltage and Current Dividers. 2. Analysis of DC Circuits. Superposition. Thevenin's and Norton's Equivalent Circuits. Node-Voltage Analysis. Loop-current Analysis. Controlled Sources. 3. The Dynamics of Circuits. Theory of Inductors and Capacitors. First-Order Transient Response of RL and RC Circuits. Advanced Transient Analysis. 4. The Analysis of AC Circuits. Introduction to Alternating Current. Representing Sinusoids with Phasors. Impedance. Phasor Diagrams for RL, RC, and RLC Circuits. 5. Circuit and System Analysis Using Complex Frequency. Complex Frequency. Impedance and the Transient Behavior of Linear Systems. Transient Response of RLC Circuits. Filters and Bode Plots. Systems. 6. Power in AC Circuits. AC Power and Energy Storage in the Time Domain. Power and Energy in the Frequency Domain. Transformers, including Electrical Safety. 7. Electric Power Systems. Three-Phase Power. Power Distribution Systems. Introduction to Electric Motors.

Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees

Abstract: As IC clock frequencies approach the GHz range, the distribution of the clock signals becomes more critical in terms of controlling both skew and signal attenuation. Moreover, inductance effects are evident since RC transmission lines will overly attenuate these high-frequency clock signals. To facilitate accurate optimization of clock tree performance and skew requires simple metrics which capture these high-frequency effects. In this paper, we derive simple metrics and bounds for the phase delay and the attenuation of a periodic [RC(L)] tree response as a function of the fundamental frequency of the clock signal. These metrics are based on the first two moments of the impulse response, and are shown to further provide a mechanism for control of underdamped responses (reflections). An important result of this work is the clear demonstration that once the attenuation of the clock signal is controlled, the phase delay can be accurately captured in terms of the first-moment. Furthermore, the form of these metrics and their relationship to one another provides an excellent foundation for various forms of clock tree optimization.

Low voltage cutoff circuit with short circuit detection capability and method of operation thereof

Abstract: A low voltage cutoff circuit, a method of operating the same and a battery backup system incorporating the low voltage cutoff circuit or the method. In one embodiment, the low voltage cutoff circuit includes: (1) a low voltage monitor coupled between an input and an output of the low voltage cutoff circuit, (2) a cutoff switch, coupled between the input and the output and controlled by the low voltage monitor, that closes to couple the input to the output, the cutoff switch subject to failing closed when a voltage of the input is below a threshold and a load couplable to the output contains a short circuit and (3) a short circuit protection circuit, coupled to the low voltage monitor, that senses when the load contains the short circuit and directs the low voltage monitor to prevent the cutoff switch from closing.

CMOS analogue median circuit

Abstract: Median filters are very important nonlinear filters, finding many applications in image and speech processing. A novel CMOS analogue median circuit is proposed with a design that employs a combination of current-mode circuits such as a current absolute value circuit and a current minimum circuit.

A fully integrated long time constant integrator circuit

Abstract: The present invention provides a long time constant integrator circuit as part of an integrated circuit. The integrator circuit is fully integrated on chip with no external capacitive or resistive components for enhancing the circuit's time constant. It achieves a -3dB cut-off frequency of 1.6Hz. The circuit is realisable on a very small area of silicon being formed by a bipolar process using npn transistors, resistive and capacitive elements. The integrator circuit comprises a transconductance stage as an input to an operational amplifier. The circuit design is fully differential and employs realisable resistors and capacitors.

Amplifier circuit and control signal generator

Abstract: By providing differential resistors in common emitters of pairs of differential transistor and differentially taking out signals from collectors, a circuit excellent in low noise property and linearity was obtained. Further, a ring type voltage controlled oscillation circuit is provided comprising n number of stages of variable delay circuits, a control signal generation circuit weighting n+1 outputs taken out of the voltage controlled oscillation circuit by a phase control signal voltage and controlling the phase, and a phase locked loop means for locking the phase by comparing the output of the voltage controlled oscillation circuit and an external pixel clock.