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Showing papers on "RC circuit published in 2000"


Journal ArticleDOI
TL;DR: In this paper, a first-order all-pass section using a single second generation current conveyor is given. And the proposed circuit is verified using PSPICE with attractive results.
Abstract: A novel first order all-pass section using a single second generation current conveyor is given. In addition the circuit uses two resistors and only one capacitor. The circuit is also realized with a translinear conveyor. The latter circuit uses only one external resistor and a capacitor. The proposed circuits are verified using PSPICE with attractive results.

132 citations


Journal ArticleDOI
TL;DR: In this paper, the effect of the absolute variation of R and C values on the phase and gain matching, as well as on the image signal suppression, was investigated for one-, two-, and three-stage networks.
Abstract: Resistance-capacitance (RC) sequence asymmetric polyphase networks have recently gained a renewed interest in the design of radio-frequency integrated transceivers. These networks provide an efficient way for wideband quadrature signal generation with reduced sensitivity to component mismatch. In addition, polyphase networks represent a passive implementation of complex analog filters used for image signal suppression. The general behavior of this class of networks, as well as their distinct property of discriminating between positive and negative sequences, are discussed and evaluated analytically. A design methodology is proposed and a sensitivity analysis based on Monte Carlo simulation is presented. The effect of the absolute variation of R and C values on the phase and gain matching, as well as on the image signal suppression, is also investigated for one-, two-, and three-stage networks.

110 citations


Proceedings ArticleDOI
01 May 2000
TL;DR: The method comprises calculating a first moment and a second moment of impulse response for an RC circuit and analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.
Abstract: An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.

99 citations


Patent
02 May 2000
TL;DR: In this paper, a method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented, which involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies.
Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor. The resistance value of the resistive transistor is modulated according to the output load current of the voltage regulator, thereby changing the location of the compensating zero.

97 citations


Patent
Xunwei Zhou1, Fred C. Lee1
13 Dec 2000
TL;DR: In this article, an interleaved small-inductance buck voltage regulator (VRM) converter with the novel current sensing and sharing technology significantly improves transient response with size minimization.
Abstract: An interleaved small-inductance buck voltage regulator (VRM) converter with the novel current sensing and sharing technology significantly improves transient response with size minimization. Specifically, two or more buck VRM modules are interleaved or connected in parallel. The resultant current waveform has a fast transient response but with reduced ripples since the ripples in the individual modules mathematically cancel one another. The result is a smooth output current waveform having spikes within an acceptable tolerance limits when for example the load increases due to a connected processor changing from “sleep” to “active” mode. A novel current sensing and sharing scheme between the individual VRMs is implemented using an RC network in each module to detect inductor current for that module. Good current sharing result can be easily achieved. Unlike peak current mode control and average current mode control, with this technology, the converter still has low output impedance and fast transient response. As a result, the VRM can be very cost-effective, high power density, high efficiency and have good transient performance.

66 citations


Proceedings ArticleDOI
05 Nov 2000
TL;DR: Simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network and frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power Distribution network are presented.
Abstract: In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

65 citations


Patent
10 Apr 2000
TL;DR: In this paper, a very small electronic device adapted for inverted mounting to a circuit board includes a multiplicity of capacitors and resistors built on a substrate, interconnected so as to provide multiple RC circuits in various circuit arrangements.
Abstract: A very small electronic device (10) adapted for inverted mounting to a circuit board includes a multiplicity of capacitors and resistors built on a substrate. The capacitors and resistors are interconnected so as to provide multiple RC circuits in various circuit arrangements. The multiple layers of the device are covered by an encapsulate having openings to expose terminal pads of the RC circuits. The openings are filled with solder to produce the individual terminations (12 and 14) of the device in a ball grid array (BGA). The device saves cost and/or board space in the manufacture of larger electronic equipment through the elimination of multiple discrete components. In addition, very low inductance is achieved due to the close proximity of the device to a circuit board on which it is mounted.

56 citations


Patent
22 Aug 2000
TL;DR: In this article, the authors describe a radio system including mixer device and switching circuit and a method having switching signal feedback control for enhanced dynamic range and performance, including a drive circuit for generating a substantially square-wave two-voltage level switching signal including phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit.
Abstract: Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance. Radio apparatus including: local oscillator input port for receiving periodic sinusoidal local oscillator signal; drive circuit for generating a substantially square-wave two-voltage level switching signal including: phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit; FET mixing device; input/output signal separation circuit; analog-to-digital converter; and feedback control circuit. Radio tuner apparatus including low-band signal processing circuit; high-band signal processing circuit including first mixer circuit operating as an up-frequency converter, amplifier circuit, second mixer circuit operating as a down-frequency converter, and feedback control circuit for adjusting a duty cycle of a mixer switching device; signal combining circuit and output processing circuit. Method for operating radio system, apparatus, and tuner. Method of operating switching circuit.

55 citations


Journal ArticleDOI
TL;DR: A new timing model, based on short-channel I-V equations, has been developed to characterize the signal delay through a resistive line and improves delay from 25% to 60% versus typical cascaded buffer methodologies.
Abstract: Repeater insertion can be used to overcome the quadratic increase in the time required for a signal to propagate through an RC interconnect. A new timing model, based on short-channel I-V equations, has been developed to characterize the signal delay through a resistive line. These analytical expressions provide the foundation for algorithms used to insert uniform repeaters into RC tree structures. Both local and global optimization algorithms for repeater insertion are presented. While the local optimization algorithm provides a computationally fast solution to the repeater insertion problem, the resulting circuit implementation is less power, area, and speed efficient than applying global optimization techniques. The global optimization algorithm for repeater insertion is achieved through the downhill simplex method. The circuit equations, algorithms, and software implementation of this repeater insertion system are presented in this paper. Results from these insertion methodologies improve delay from 25% to 60% versus typical cascaded buffer methodologies. Global repeater insertion further decreases delay times by up to 22% over the local repeater insertion method. The accuracy of the timing model characterizing the repeater insertion process as compared to SPICE simulations is generally within 10%. Applications of these algorithms for minimizing the signal delay through an RC tree, such as in data paths, and targeting signal delays through an RC tree, such as in clock distribution networks, are also discussed.

43 citations


Journal ArticleDOI
TL;DR: This paper shows how genetic programming can be used to automate the design of eight prototypical analog circuits, including a lowpass filters, a highpass filter, a bandstop filter, an tri-state frequency discriminator circuit, a frequency-measuring circuit, an 60 dB amplifier, a computational circuit for the square root function, and a time-optimal robot controller circuit.

37 citations


Journal ArticleDOI
TL;DR: A new universal biquadratic filter configuration using two current-feedback amplifiers (CFAs) is presented and can realize all the standard filter functions, that is, highpass, bandpass, lowpass, notch, and allpass filters, without changing the passive elements.
Abstract: A new universal biquadratic filter configuration using two current-feedback amplifiers (CFAs) is presented. The circuit has three inputs and one low-impedance output and can realize all the standard filter functions, that is, highpass, bandpass, lowpass, notch, and allpass filters, without changing the passive elements. The proposed circuit has no requirements for component matching conditions and uses only four passive components. The center frequency and bandwidth can be orthogonally controllable. Also, the active and passive sensitivities are low.

Patent
Gyu-Hyeong Cho1, Gyun Chae1
28 Jul 2000
TL;DR: In this paper, a power-factor correction circuit of an electronic ballast for fluorescent lamps is presented, which includes an input full-wave rectification circuit for rectifying an input voltage from an AC input power source, a DC-link capacitor for supplying a DClink voltage in response to an output voltage from the rectification circuits, and a resonant inverter connected in parallel to the DClink capacitor.
Abstract: A power-factor correction circuit of an electronic ballast for fluorescent lamps which includes an input full-wave rectification circuit for full-wave rectifying an AC input voltage from an AC input power source, a DC-link capacitor for supplying a DC-link voltage in response to an output voltage from the rectification circuit and a resonant inverter connected in parallel to the DC-link capacitor. The power-factor correction circuit comprises a charge pumping circuit disposed between the AC input power source and the rectification circuit, a valley-fill DC voltage supply circuit disposed between the rectification circuit and the DC-link capacitor, and a high-frequency full-wave rectification circuit disposed between the DC voltage supply circuit and the DC-link capacitor and connected to a secondary winding of a power transformer in the resonant inverter. The high-frequency full-wave rectification circuit includes a first pole connected to the secondary winding of the power transformer and a second pole connected to a common connection point of a plurality of stabilizing capacitors connected in series respectively to the fluorescent lamps. Therefore, a power factor of the ballast is improved and power supply is automatically controlled according to the number of fluorescent lamps being turned on.

Patent
22 Nov 2000
TL;DR: In this paper, a circuit and method for regulating a voltage by means of a switched capacitor circuit including multiple switches and capacitors is presented, which is operable in a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load.
Abstract: A circuit and method for regulating a voltage by means of a switched capacitor circuit including multiple switches and capacitors. The circuit is operable in a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels. In addition, the circuit provides lower output ripple than conventional charge pumps.

Journal ArticleDOI
01 Oct 2000
TL;DR: In this paper, the authors present general guidelines for the design of the oscillation-based test structures and describe in more detail test transformations of filter configurations which are most frequently used in practice.
Abstract: The oscillation test methodology is presented for active RC filters. The authors develop general guidelines for the design of the oscillation-based test structures and describe in more detail test transformations of filter configurations which are most frequently used in practice. Frequency measurements performed on some implemented test structures and fault detection experimental results are included. The oscillation-based test described in the paper is primarily intended for field testing. In some cases, it can also be used as a functional go no-go test in production. The presented test structures can also be employed for stimulus generation in a built-in self-test.

Patent
James B. Burr1
19 Oct 2000
TL;DR: In this article, a method for providing low power MOS devices that include buried wells specifically designed to provide a resistive path between the bulk material of the device and a well tie contact was proposed.
Abstract: A method for providing low power MOS devices that include buried wells specifically designed to provide a resistive path between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between clock cycles.

Journal ArticleDOI
TL;DR: In this paper, two variations of a continuous-time instantaneous companding filter were integrated in a 25 GHz bipolar process, and their -3dB frequencies were tunable in the ranges of 1-30 and 30-100 MHz.
Abstract: Two variations of a continuous-time instantaneous companding filter were integrated in a 25 GHz bipolar process. Their -3-dB frequencies are tunable in the ranges of 1-30 and 30-100 MHz. The DC gains are controllable up to 10 dB. The measured dynamic ranges for a 1% total harmonic distortion are 62.5 and 50 dB, for the 30 and 100 MHz filters, respectively. At maximum cutoff frequencies, the filters dissipate 6.5 mW from a 1.2 V supply.

Patent
29 Feb 2000
TL;DR: In this article, an RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage of the capacitor after a predetermined time has expired since the capacitor began charging up.
Abstract: An RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage on the capacitor after a predetermined time has expired since the capacitor began charging up. The result of the comparison, which indicates whether the voltage on the resistor is greater than the voltage on the capacitor, is then used to adjust the capacitance of the capacitor to servo the RC time constant to a predetermined value.

Patent
John E. Carlson1
22 Jun 2000
TL;DR: An output amplifier for a strobed sampling circuit has first and second operational amplifiers coupled to receive the sampled output from the sampling circuit as discussed by the authors, which are closed at a predetermined time interval to discharge the stored charge on the capacitors prior to the next strobe pulse.
Abstract: An output amplifier for a strobed sampling circuit has first and second operational amplifiers coupled to receive the sampled output from the sampling circuit. The operational amplifiers each have a RC circuit having a high ohmic value resistor that is coupled from its inverting input terminal to its output terminal. The non-inverting input terminals receive biasing voltages that are coupled to the sampling circuit. The gating strobes to the sampling circuit produces a DC current through the feedback resistor as a result of strobe pulses being integrated by the RC circuit. Respective electronic switches are coupled in parallel with the RC circuits of the operational amplifiers and are closed at a predetermined time interval after each strobe pulse to discharge the stored charge on the capacitors prior to the next strobe pulse. The output signals from the operational amplifiers are summed in a summing amplifier.

Patent
14 Jan 2000
TL;DR: In this paper, a bias circuit is configured with components identical to those for a CMOS inverter to constitute an input circuit, and the output from the input circuit is latched by a latch circuit 18 to prevent malfunction of peripheral circuits.
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing unit with a small chip area and a stable circuit characteristic. SOLUTION: A bias circuit is configured with components identical to those for a CMOS inverter to constitute an input circuit. Thus, even when the signal input circuit is affected by a manufacturing provided or external factors or the like, a DC voltage V1 that is outputted from the bias circuit and on which an AC input signal Vin is superimposed and threshold voltages VIH, VIL of the input circuit have similar variations, thus a stable circuit characteristic is obtained. Furthermore, NMOS TRs 17, 23 are subject to on/off control properly by 1st and 2nd control signals to stop a through-current of the bias circuit and the input circuit thereby reducing the current consumption. Even when operation of the input circuit is stopped, the output from the input circuit is latched by a latch circuit 18 to prevent malfunction of peripheral circuits.

Journal ArticleDOI
TL;DR: These realizations are based on the simplest possible models for second-order RC sinusoidal oscillators that are used to replace the active tank resonator in the classical Chua's circuit configuration.
Abstract: We propose novel generic RC realizations of Chua's circuit. These realizations are based on the simplest possible models for second-order RC sinusoidal oscillators that are used to replace the active tank resonator in the classical Chua's circuit configuration. The sinusoidal oscillators are represented by circuit-independent black-box models. Hence, numerous circuit realizations can be derived.

Patent
01 Sep 2000
TL;DR: In this article, a FET controlled AC/DC power conversion circuit and application of the same is presented, where the entire conversion circuit is constituted by a rectifier circuit, a switching circuit consisting of an FET, a controlling circuit, and a voltage stabilizing circuit.
Abstract: Disclosed herein is a FET controlled AC/DC power conversion circuit and application of same. The entire conversion circuit is constituted by a rectifier circuit, a switching circuit consisting of a FET, a controlling circuit, a monitor circuit, and a voltage stabilizing circuit, wherein output voltages of the rectifier circuit is respectively sent to the switching circuit and the controlling circuit, where switching time of the switching circuit is controlled by the controlling circuit thereby achieving control of output voltage to a load or loads.

Proceedings ArticleDOI
10 Jun 2000
TL;DR: In this paper, a 0.6 /spl mu/m BiCMOS analog baseband IC that enables a direct conversion W-CDMA receiver is described, and two diversity I/Q channels provide 87 dB of voltage gain, controllable in 1-dB steps.
Abstract: A 0.6 /spl mu/m BiCMOS analog baseband IC that enables a direct conversion W-CDMA receiver is described. Two diversity I/Q channels provide 87 dB of voltage gain, controllable in 1-dB steps. A 2 MHz low pass filter, synchronized to an external RC network, provides an accurate rejection mechanism against adjacent channel interference. A log amp provides a "Fast-RSSI" function for rapidly selecting gain settings. Low DC current (<5 mA/path), low input noise (<4 nV/Hz/sup 1/2/), and a high P3dB (-20 dBVrms) are achieved.

Journal ArticleDOI
H. Ishikawa1, Y. Murai
TL;DR: In this paper, a series resonant (current resonant) DC link inverter with a voltage clamped circuit has been proposed, which has a fixed pulse frequency operation at 20-50 kHz.
Abstract: This paper develops a new series resonant (current resonant) DC link inverter with a voltage clamped circuit. The proposed circuit has a fixed pulse frequency operation. The fixed pulse frequency at 20-50 kHz enables the system to work without audible noise, and to involve the much smaller-sized DC inductance and output capacitors compared with hard-switched current source inverters. The proposed circuit has a voltage clamped circuit which could control the voltage stress of the switches. In this paper, explanations of the new circuit configuration, the simulation, design considerations, and some experimental results are included.

Patent
Agnes Woo1
29 Jun 2000
TL;DR: In this paper, a circuit for applying power to mixed-mode integrated circuits in a predefined sequence is described, which includes a first circuit powered by a first voltage and a second circuit powered with a second voltage that is less than the first voltage.
Abstract: A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltage coupled to the first circuit. The circuit for applying power to mixed mode integrated circuits includes, a modified IO cell of the second circuit. The modified IO cell has a driver transistor including a back gate terminal, a gate terminal that is driven by the second circuit, a source terminal that is coupled to a first circuit signal, and a drain terminal that is coupled to the second power supply. The circuit for applying power to mixed mode integrated circuits further includes, a controller circuit coupled to the first voltage and the second voltage supplied as controller circuit inputs. The controller circuit has a plurality of controller circuit outputs. The circuit for applying power to mixed mode integrated circuits also includes, a back gate bias application circuit. The back gate bias application circuit has a plurality of inputs coupled to the plurality of controller circuit outputs, and an output coupled to the backgate of the driver transistor backgate terminal.

Journal ArticleDOI
01 Feb 2000
TL;DR: In this paper, continuous-time active RC filters can be implemented in CMOS by replacing all resistors by MOSFETs operating in the linear region, as long as the specifications for frequency, pole-Q, spurious-free dynamic range and supply voltage lie within certain limits.
Abstract: The authors show how continuous-time active-RC filters can be implemented in CMOS by replacing all resistors by MOSFETs operating in the linear region. As an example, a 24 MHz active MOSFET-C single-amplifier biquadratic lowpass filter with a pole-Q of 3 implemented in a 0.6 /spl mu/m CMOS process is discussed. By comparing measurements of a test chip, simulations and calculations, the following conclusion is reached. As long as the specifications for frequency, pole-Q, spurious-free dynamic range and supply voltage lie within certain limits, then active-MOSFET-C single-amplifier biquads (MOSFET-C SABs) are preferable; with respect to chip size and power consumption, compared to multi-amplifier biquads, e.g. integrator-connected biquads. Above these limits, the latter must be used.

Patent
Tomohiro Kawakubo1
28 Feb 2000
TL;DR: In this article, an internal voltage generation circuit with a small area, which has many correction points and can provide an output voltage with a high precision, has been disclosed, where some resistors have different resistance and transfer gates are provided in parallel to the resistors of different resistance.
Abstract: An internal voltage generation circuit with a small area, which has many correction points and can provide an output voltage with a high precision, has been disclosed. In this internal voltage generation circuit, some resistors, among the resistors which are connected in series constituting the feedback circuit, have different resistance and transfer gates are provided in parallel to the resistors of different resistance. This configuration has a decode function and, therefore, the decoder can be eliminated and the number of sets of an inverter, a transfer gate, and a resistor can also be reduced, resulting in a reduction in area without a reduction in the number of the correction points.

Patent
15 Nov 2000
TL;DR: A balancing circuit for voltages of a series-connection of capacitors, particularly for intermediate circuit capacitors of an inverter, is described in this paper, where there are at least two series-connected intermediate circuits capacitors across an intermediate circuit voltage.
Abstract: A balancing circuit for voltages of a series-connection of capacitors, particularly for intermediate circuit capacitors of an inverter, there being at least two series-connected intermediate circuit capacitors across an intermediate circuit voltage, the balancing circuit comprising a converter circuit which in turn comprises a transformer (T1) a primary winding of which is divided into capacitor-specific part-windings (N11, N12), a secondary winding (N2) being connected to provide voltage supply. The converter circuit of the balancing circuit comprise sub-converters connected in parallel with each series-connected capacitor (C1, C2), each one of the sub-converters comprising a series connection of a part-winding (N11, N12) of the primary winding, a diode (D1, D2) and a semiconductor switch (V1, V2) to be controlled for balancing the voltages of the series-connected capacitors.

Patent
23 Mar 2000
TL;DR: In this paper, a preamplifier circuit was used to detect the mean value of a received signal in one byte of the data of a 10 Gb/s optical receiving circuit.
Abstract: An optical receiving circuit 1 is composed of a preamplifier circuit 2, an output differential amplifier 3 and a mean value holding circuit 4. The optical receiving circuit 1 is connected to a photodetector 5 for receiving an input optical signal and outputting current. For the preamplifier circuit 2, a transimpedance type circuit may also be used. The preamplifier circuit 2 comprises a feedback resistor 21 and a resistor for detecting output voltage 22, the transimpedance gain is 55 dB Ω and 3 dB bandwidth when the photodetector 5 the capacity of which is 0.2 pF is connected to its output is 8 GHz. The output differential amplifier 3 discriminates and regenerates data by regulating reference voltage Vref between the high level and the low level of the amplitude of an input signal. The mean value holding circuit 4 includes a sample-hold circuit 41 and capacity 42 for holding the mean value of voltage output from the preamplifier circuit 2. As a CR time constant based upon the capacity 42 and the resistor for detection 22 is 1 ns., the mean value level of a received signal can be detected in approximately one byte of the data of 10 Gb/s. The sample-hold circuit 41 samples the detected mean value level according to a sampling pulse from an external device and holds it. The output of the sample-hold circuit 41 is used for the reference voltage of the differential amplifier 3.

Proceedings ArticleDOI
08 Aug 2000
TL;DR: It is demonstrated that on-chip signals can be approximated by a Fourier series up to the 15th harmonic component as well as the effective load impedance characterizing a distributed RC and RLC line driven by a CMOS logic gate.
Abstract: A Fourier analysis of on-chip signals in CMOS integrated circuits is presented in this paper. It is demonstrated that on-chip signals can be approximated by a Fourier series up to the 15th harmonic component. The effective load impedance characterizing a distributed RC and RLC line driven by a CMOS logic gate is based on a Fourier analysis of the on-chip signals. The voltage waveform based on the effective load impedance approaches a distributed RC and RLC line approximated by sections of lumped RC and RLC elements.

Patent
21 Sep 2000
TL;DR: A balancing circuit for voltages of a series connection of capacitors, particularly for intermediate circuit capacitors of an inverter, was proposed in this article, where the input poles of which are connected in parallel with the capacitor corresponding to the inverter and the output poles of the corresponding poles of a voltage source (Va).
Abstract: A balancing circuit for voltages of a series connection of capacitors, particularly for intermediate circuit capacitors (3) of an inverter, there being at least two intermediate circuit capacitors connected in series over intermediate circuit voltage. The balancing circuit comprises capacitor-specific freely oscillating inverters (4), the input poles of which are connected in parallel with the capacitor corresponding to the inverter and the output poles of which are connected in parallel to provide a voltage source (Va).