Showing papers on "RC circuit published in 2001"

Construction of classes of circuit-independent chaotic oscillators using passive-only nonlinear devices

Abstract: Two generic classes of chaotic oscillators comprising four different configurations are constructed. The proposed structures are based on the simplest possible abstract models of generic second-order RC sinusoidal oscillators that satisfy the basic condition for oscillation and the frequency of oscillation formulas. By linking these sinusoidal oscillator engines to simple passive first-order or second-order nonlinear composites, chaos is generated and the evolution of the two-dimensional sinusoidal oscillator dynamics into a higher dimensional state space is clearly recognized. We further discuss three architectures into which autonomous chaotic oscillators can be decomposed. Based on one of these architectures we classify a large number of the available chaotic oscillators and propose a novel reconstruction of the classical Chua's circuit. The well-known Lorenz system of equations is also studied and a simplified model with equivalent dynamics, but containing no multipliers, is introduced.

Thermal component model for electrothermal analysis of IGBT module systems

Abstract: The insulated gate bipolar transistor (IGBT) modules are getting more accepted and increasingly used in power electronic systems as high power and high voltage switching components. However, IGBT technology with high speed and greater packaging density leads to higher power densities on the chips and increases higher operating temperatures. These operating temperatures in turn lead to an increase of the failure rate and a reduction of the reliability. In this paper, the static and dynamic thermal behavior of IGBT module system mounted on a water-cooled heat sink is analyzed. Although three-dimensional finite element method (3-D FEM) delivers very accurate results, its usage is limited by an imposed computation time in arbitrary load cycles. Therefore, an RC component model (RCCM) is investigated to extract thermal resistances and time constants for a thermal network. The uniqueness of the RCCM is an introduction of the time constants based on the Elmore delay, which represents the propagation delay of the heat flux through the physical geometry of each layer. The dynamic behavior predicted by the thermal network is equivalent to numerical solutions of the 3-D FEM. The RCCM quickly offers insight into the physical layers of the components and provides useful information in a few minutes for the arbitrary or periodic power waveforms. This approach enables a system designer to couple the thermal prediction with a circuit simulator to analyze the electrothermal behavior of IGBT module system, simultaneously.

Low-power low-jitter variable delay timing circuit

Abstract: The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line to a voltage on a current control node connected to a voltage controlled current source. An RC compensating circuit may be coupled to the current control node.

The origin of the kink phenomenon of transistor scattering parameter S/sub 22/

Abstract: A novel theory based on dual-feedback circuit methodology is proposed to explain the kink phenomenon of transistor scattering parameter S/sub 22/. Our results show that the output impedance of all transistors intrinsically shows a series RC circuit at low frequencies and a parallel RC circuit at high frequencies. It is this inherent ambivalent characteristic of the output impedance that causes the appearance of kink phenomenon of S/sub 22/ in a Smith chart. It was found that an increase of transistor transconductance enhances the kink effect while an increase of drain-to-source (or collector-to-emitter) capacitance obscures it. This explains why it is much easier to see the kink phenomenon in bipolar transistors, especially heterojunction bipolar transistors, rather than in field-effect transistors (FETs). It also explains why the kink phenomenon is seen in larger size FETs and not in smaller size FETs. Our model not only can predict the behavior of S/sub 22/, but also calculate all S-parameters accurately. Experimental data of submicrometer gate Si MOSFETs and GaAs FETs are used to verify our theory. A simple method for extracting transistor equivalent-circuit parameters from measured S-parameters is also proposed based on our theory. Compared with traditional Z- or Y-parameter methods, our theory shows another advantage of giving deep insight into the physical meaning of S-parameters.

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

Abstract: A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm/sup 2/ was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 /spl mu/V and 47 /spl mu/V in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V.

High accuracy timing model for integrated circuit verification

Abstract: A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive ('RC') network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.

A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs

Abstract: We propose a physically acceptable small-signal model incorporating substrate effects, in order to eliminate the severe frequency-dependence of the intrinsic drain-source resistance observed from a conventional model of RF Si MOSFETs. This model is based on the substrate network where a parallel RC circuit is connected in series with the drain junction capacitance. It is demonstrated that the substrate effects result in the frequency-dispersion of the effective drain-source resistance and capacitance below 10 GHz. An accurate extraction technique using a simple curve-fit approach is developed to determine substrate parameters directly, and their bulk voltage-dependencies are presented in detail. The validity of this model is partially proved by finding intrinsic parameters exhibiting frequency-independence up to 10 GHz. Better agreement with measured S-parameters is achieved by using the new substrate model rather than the conventional one, verifying the accuracy of the physical model and extraction technique.

Low-dropout voltage regulator with improved stability for all capacitive loads

Abstract: The present invention provides an LDO that is stable for all capacitive loads. Because the LDO is stable for all capacitive loads, the ESR (equivalent series resistance) inherent in any capacitive load can no longer affect the equivalent value of the combination of the ESR and the capacitive load. Thus, the invention also effectively removes the ESR restrictions on the loads. According to the present invention, a low dropout voltage regulator is provided. The regulator comprises a switching element (e.g., a transistor) having first terminal for receiving an input signal, a second terminal for providing an output signal and a control terminal; a control circuit, operably coupled to the switching element, that is configured to control the switching element; and a compensation circuit having a first segment connected between the first and control terminals of the switching element and a second segment connected between the control and second terminals of the switching element. The first segment of the compensation circuit includes a first resistor and the second segment of the compensation circuit includes a RC circuit. In one embodiment of the invention, the RC circuit includes a second resistor and a capacitor connected to each other in series. In another embodiment of the invention, the RC circuit includes a distributed RC network having a plurality of resistors and capacitors.

Method and apparatus for a DC-DC charge pump voltage converter-regulator circuit

Abstract: An apparatus and method for a DC-DC charge pump voltage converter-regulator circuit includes a control circuit, a multiplier circuit, and a feedback circuit. The feedback circuit includes a load circuit, a comparator circuit, and a voltage reference circuit. The multiplier circuit produces an output signal by multiplying a supply signal according to a multiplication factor. The output signal is communicated to the load circuit. The output signal is measured producing a sense signal. The voltage reference circuit produces a reference voltage. The control circuit regulates the output signal according the result of a comparison between the sense signal and the reference voltage. In one embodiment, the multiplication factor is adjusted to compensate for a change in the supply signal. The multiplication factor may be increased to compensate for a decrease in the supply signal.

Facility to measure solar cell ac parameters using an impedance spectroscopy technique

Abstract: An experimental setup has been developed to measure the solar cell ac parameters using an impedance spectroscopy technique. It consists of an electrochemical interface to set the dc bias voltage and to apply the signal voltage across the solar cell and a frequency response analyzer to generate the excitation signal with varying frequency and analyze the result. The setup is calibrated with a standard RC network and measured an error of ±4% (maximum). Solar cell capacitance, parallel resistance and series resistance are calculated from the measured data.

Method and circuit for testing dc parameters of circuit input and output nodes

Abstract: A method and built-in circuit are described for testing direct current (DC) parameters of the input and output pins of a circuit by testing the transition time interval for rising and falling voltage transitions. When the voltage transition is for an integrated circuit (IC) pin having a known capacitance, which can include off-chip capacitance, the magnitude and direction of current at the pin can be determined. The method enables testing an IC via a test access port (TAP) comprising a subset of the pins of the IC, for example in conformance with the IEEE 1149.1 boundary scan test standard. For sufficiently small current magnitudes, such as leakage current (IIL and IIH), the technique can use only on-chip circuitry to sample a pin voltage at time intervals after an output transition is generated at the pin, the time intervals pre-determined to be less than the transition time interval. For larger current magnitudes, such as IOL and IOH, an off-chip capacitance of known value is connected to the pin to decrease the rate of transition. For greater accuracy, an off-chip resistor of known value is connected to the pin, and the transition time interval due to the driver is compared to the transition time interval due to the resistor.

Micropower RC oscillator

Abstract: A micropower RC oscillator having stable frequency characteristics with varying temperature includes a number of inverting circuits which are driven by an external driving voltage and connected in series with each other and an RC circuit having a resistor disposed in between a head-inverter and a tail inverter to form a closed loop and a capacitor disposed between the tail-inverter and the head-inverter. The resistor comprises a plurality of unit resistors constituting of a P+ diffusion resistor and a polysilicon resistor having opposing characteristics with respect to temperature variation at a predetermined ratio. A resistance regulator controls the resistance of the resistor by decoding an external resistance setting data to select a unit resistor that determines the oscillation frequency effectively. A driving voltage circuit receives a reference signal having the voltage level which is stable against the temperature variation by using a current source and a load having opposing characteristics with respect to the temperature variation and provides as a driving voltage of the RC oscillating circuit after increasing a fan-out capacity of the reference signal. An output level shifting circuit can be added to the rear side of the RC oscillating circuit to adjust the voltage level of the oscillation signal with the appropriate standard required at a receiving end.

Level shift circuit and semiconductor integrated circuit

Abstract: A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

VCO circuit with wide output frequency range and PLL circuit with the VCO circuit

Abstract: A voltage-controlled oscillating circuit according to the present invention includes: a bias voltage generating circuit outputting a bias voltage according to a control voltage; and a ring oscillator circuit receiving supply of the bias voltage to operate. The bias voltage generating circuit generates the bias voltage using a feedback circuit formed by an operational amplifier receiving supply of a power source voltage to operate. Therefore, an influence of a high frequency component overlapped on the power source voltage, that is an influence of noise, is suppressed, thereby enabling stable generation of an output clock having a small variation in phase.

Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device

Abstract: An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto-calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset voltage compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compensation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit. The digital control circuit switches the inputs, the output and feedback-gain determining resistors for the analog input device during a calibration mode. A voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the digital control circuit by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage.

Delay and current estimation in a CMOS inverter with an RC load

Abstract: A novel and efficient method is presented for computing the delay and supply current pulse in a CMOS inverter with an RC load. The method builds on existing techniques for computing these quantities in the presence of a capacitance load. As in the work of other authors, the concept of an effective capacitance C/sub eff/ is used. However, here it captures the inverter's behavior only while the charging/discharging transistor is in saturation and, therefore, behaves like a current source to a good approximation. This capacitance is determined by means of a simple iterative procedure that uses an empirical piecewise-linear approximation to the RC circuit's output voltage, which has a normal CMOS symmetrical form. Since a C/sub eff/ defined in the above way is independent of the inverter's parameters, such as transistor size, the coefficients of the approximation have to be determined for only one reference inverter. A simple analytical method yields the inverter's output voltage outside the saturation region. The complete model has been shown to be accurate for both 0.8-/spl mu/m 5-V and 0.24-/spl mu/m 2.5-V CMOS technologies. Its speed is comparable to that of the "capacitance load" techniques that it relies on.

Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation

Abstract: In today's deep submicrometer technology the coupling capacitances among individual on-chip RC trees have an essential effect on the signal delay and crosstalk, and the interconnects should be modeled as coupled RC trees. In this paper we provide simple exact explicit formulas for the Elmore delay and higher order voltage moments and a linear order recursive algorithm for the voltage moment computation for lumped and distributed coupled RC trees. By using the formulas and algorithms, the moment-matching method can be efficiently implemented to deal with delay and crosstalk estimation, model order reduction, and optimal design of interconnects. As an application of the algorithm, we provide a new efficient and accurate model for crosstalk estimation in coupled RC trees. Simulation results show it works better than existing methods.

Low-distortion differential circuit

Abstract: A differential feedback system that minimizes even order distortion of a differential circuit. The feedback system includes a feedback circuit for use with a differential circuit to reduce even-order distortion and dc offset of a difference output signal produced by the differential circuit. The feedback circuit includes an integrator coupled to receive the difference output signal from the differential circuit and produce an integrator output signal. The feedback circuit also includes a control circuit coupled to the integrator to receive the integrator output signal to produce a control signal that is coupled to the differential circuit, wherein the control signal controls the differential circuit to reduce the even-order distortion and the DC offset.

Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit

Abstract: The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣC ch,↑ (nT) and ΣC ch,↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Z d and Z g of the source line and the ground line.

Modeling CMOS gates driving RC interconnect loads

Abstract: The problem of estimating the performance of CMOS gates driving RC interconnect loads is addressed in this paper. The widely accepted /spl pi/-model is used for the representation of an interconnect line that is driven by an inverter. The output waveform and the propagation delay of the inverter are analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, short-circuit power dissipation is accurately estimated. Once the voltage waveform at both the beginning and the end of an interconnect line are obtained, a simple method is employed in order to calculate the voltage waveform at each point of the line.

Low-frequency differentiators and integrators for biomedical and seismic signals

Abstract: A general active-network synthesis approach to inverse system design is introduced. The approach is applied to a passive RC differentiator and a passive RC integrator to obtain, respectively, a very low-frequency differential integrator and a very low-frequency differential differentiator. The frequency ranges of the proposed circuits, from dc to a few hundred hertz, are particularly suitable to the frequency ranges of biomedical and seismic signals. The advantages of the proposed circuits are delineated and include single time constants, dc stable integrators, and resistive input differentiators. Noninverting and inverting differentiators and integrators could be obtained by grounding one of the input terminals in the differential configurations.

Central symmetric gamma voltage correction circuit

Abstract: A central symmetric Gamma voltage correction circuit is mainly applied to the displaying circuit of liquid-crystal display. By installing a resistor voltage dividing circuit and a driving circuit so that a well adjustment way to the Gamma correction voltage can be acquired. Moreover, the value of the Gamma correction voltage is controlled by externally inputting voltage, and thus the number of external correction reference voltage input externally and the number of the amplifiers are reduced. The resistor voltage dividing circuit and driving circuit are formed by a plurality of resistors, adjustable resistors and amplifiers so as to achieve the object of reducing the number of externally inputting correction voltages and the number of amplifiers.

Batch mode micro-EDM for high-density and high-throughput micromachining

Abstract: This paper examines scaling issues for electrode arrays used in micro-electro-discharge machining (micro-EDM). In particular, it explores constraints in the fabrication and usage of high aspect ratio LIGA-fabricated electrode arrays, as well as the limits imposed by the pulse discharge circuits on machining rates. A LIGA-fabricated array of 400 Cu electrodes with 20 /spl square/m diameter was used to machine through-holes in 50 /spl square/m thick stainless steel. An array of multi-layer structures that included tapered shapes was fabricated by the sequential use of three electrode arrays of varying shape. The electrode fabrication and usage for these efforts are described. With respect to the pulse discharge circuits, it is shown that the machining time can be reduced by >50% by dividing the electrode array into sections have independent control of pulse discharge timing. This is implemented by using individual RC timing circuits for each section. A correlation between electrode area per RC circuit and machining rate is described.

Crosstalk noise estimation for generic RC trees

Abstract: We propose an estimation method of crosstalk noise for generic RC trees. The proposed method derives an analytic waveform of crosstalk noise in a 2-/spl pi/ equivalent circuit. The peak voltage is calculated from the closed-form expression, and the crosstalk induced delay is estimated using the derived noise waveform. We also develop a transformation method from generic RC trees with branches into the 2-/spl pi/ model circuit. The proposed method can hence estimate crosstalk noise for any RC trees. Our estimation method is evaluated in a 0.13 /spl mu/m technology. The peak noise of two partially-coupled interconnects is estimated with the average error of 13%. Our method transforms generic RC interconnects with branches into the 2-/spl pi/ model with 14% error on average.

Disk reproducing apparatus having active wide-range PLL device

Abstract: This invention prepares two control voltage to be input to a VCO circuit. The first control voltage is used to continuously change the oscillation frequency of the VCO circuit. The second control voltage is used to continuously change the first control voltage/oscillation frequency characteristics. The invention also includes a phase detecting circuit for comparing the phase of the data read from a disk with that of the output from the voltage-controlled oscillator, a frequency detecting circuit for comparing the frequency of the data read from the disk with that of the output from the voltage-controlled oscillator, a first filter circuit for equalizing signals representing the detection results obtained by the phase detecting circuit and the frequency detecting circuit, and a second filter circuit for extracting only a low-frequency component from the output from the first filter circuit. The output from the first filter circuit is used as the first control voltage. The output from the second filter circuit is used as the second control voltage. The second control voltage is changed to always keep the first control voltage at a predetermined voltage.

Source voltage conversion circuit and its control method, display, and portable terminal

Abstract: A source voltage conversion circuit comprising a charge pump circuit with switching devices (a N-ch MOS transistor Qn (12) and a P-ch MOS transistor Qp (12)) in the output section wherein a switching pulse voltage (control pulse voltage) for the switching devices is diode-clamped by a first clamp circuit (13) when the source voltage conversion circuit is started, and wherein the switching pulse voltage is clamped to a ground level (negative side circuit source potential) by a second clamp circuit (16) on the basis of a clamp pulse comprising an output voltage Vout when a starting process is ended, so that a sufficient drive voltage particularly for the Pch-MOS transistor Qp(12) is obtained. This constitution provides a source voltage conversion circuit which can obtain a large current capacity with a small area circuit scale and its control method, a display loaded with the source voltage conversion circuit as the power circuit, and a portable terminal comprising this display.

Voltage stabilization circuit

Abstract: A voltage stabilization circuit includes a band gap reference circuit to generate a stable output voltage that is temperature-independent, and a folded cascode feedback circuit to generate a feedback potential that is applied to stabilize the band gap reference circuit. The folded cascode feedback circuit is implemented with current mirror circuits.

Use of current folding to improve the performance of a current -steered DAC operating at low supply voltage

Abstract: The performance of a single-bit cell in a DAC is improved by decoupling the voltage swing across the load resistors from the output of the current steering device. This can be achieved by providing for a single-bit cell having a first load resistor R1 and a second load resistor R2, a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R1, R2. The current steering circuit steers at least part of a current I1 through a circuit path towards either the first resistor R1 or the second resistor R2. The decoupling circuit decouples voltage swings across the load resistors R1, R2 from the current steering circuit.

Rigorous event-driven (RED) analysis of large-scale nonlinear RC circuits

Abstract: Event-driven methods are very promising for simulating large-scale linear and nonlinear circuits but they may suffer some drawbacks, such as spurious numerical oscillations and have difficulties in convergence to equilibrium points. To overcome these drawbacks a pseudoanalytical method is presented that is based on the staircase approximation of v-i characteristics of linear and nonlinear resistors, on the piecewise-linear approximation of v-q characteristics of nonlinear capacitors and t-v characteristics of time-varying voltage sources. At a generic time instant, these approximations allow us to represent the original circuit with a very simple model composed of only linear capacitors, voltage and current sources. The solution of this circuit model is straightforward but, when the operating point meets some pathological situations, the model does no longer hold and then a rigorous and in general more complex analysis is needed. Even if this analysis yields a conceptual effort, its computational execution is not complex. This algorithm works successfully on circuits composed of linear and nonlinear resistors and capacitors, time-varying voltage and time-invariant current sources. Some applications of this method to the analysis of interconnects and power-grids in VLSI circuits are presented.

Converting circuit for providing operating points in a central processor unit

Abstract: A converting circuit for providing operating points in a central processor unit (CPU) applying suitable resistor-capacitor (RC) circuits in the computer system. The resistance and capacitance in the RC circuits are designed to generate the needed operating frequency and voltage in the CPU. The conversion of the operating frequency and voltage is designed to be steady and synchronous so that the surge current occurring in the prior art can be reduced, thereby lowering cost.