Showing papers on "RC circuit published in 2002"

Practical oscillation-based test of integrated filters

Abstract: Oscillation-based test (OBT) techniques show promise in detecting faults in mixed-signal circuits and require little modification. to the circuit under test. Comparing both the oscillation's amplitude and frequency yields acceptable test quality. OBT seems especially appealing for filters but requires adaptation to handle monolithic circuits or the analog-core-based design of complex mixed-signal ICs.

Fault-tolerant multi-point flame sense circuit

Abstract: A fault-tolerant multi-point flame sense circuit utilizes a single electronic switch to signal the presence or absence of flame to an electronic controller. Multiple flame sense electrodes may be input to this circuit. By configuring these electrodes in accordance with the present invention, cross-contamination of a single failed flame sense electrode will not affect the other flame sense electrodes' ability to sense a flame at their associated burner. The circuit provides inputs for a number of flame sense electrodes via input channels that are capacitively coupled to the line voltage and resistively coupled to an RC network that controls the state of an electronic switch. When a flame is present at any one of the electrodes, the resulting unbalance current flow through the RC network turns the switch off to indicate the presence of flame. This operation is not affected by a short on any other electrode in the circuit.

A novel equivalent circuit and modeling method for defected ground structure and its application to optimization of a DGS lowpass filter

Abstract: In this paper, a novel equivalent circuit and modeling method for a defected ground structure is proposed to design an optimized DGS lowpass filter circuit The equivalent circuit presented in this paper has parallel capacitance to explain the fringing fields due to the defects on the metallic ground plane Several comparisons between the EM-simulations on the DGS circuits and circuit simulations on its equivalent circuits are demonstrated to show the validity of the proposed model Optimization for the DGS circuit is carried out by using the proposed equivalent circuit Simulation and measurements on the fabricated DGS lowpass filter show optimized passband and stopband performance

Method and apparatus for filter tuning

Abstract: Tuning of a filter circuit is accomplished by determining a real RC time constant value for the filter circuit, then comparing the real RC vale to a predetermined RC value. If the real RC value does not match the predetermined RC value, the real RC value is varied (e.g., using a number of capacitors in a capacitor array).

Method and apparatus for trimming current limit and frequency to maintain a constant maximum power

Abstract: A method which regulates a power supply is disclosed. In one aspect of the invention, the method includes sensing an excess control current through a control terminal with a control current sensor circuit. A transistor is switched with a control circuit in response to the control current sensor circuit and an oscillator that is coupled to a trim circuit, which is trimmed during manufacture of a circuit, to regulate the output of a power supply. A current through the transistor is limited with a current limit circuit that is coupled to the trim circuit, which is trimmed during manufacture of the circuit. A maximum deliverable power value of the power supply is determined by said trimming of the trim circuit during manufacture of the circuit.

Battery characterization system

Abstract: A system for modeling a lead-acid battery is disclosed. A system for modeling a lead-acid battery is also disclosed. An equivalent circuit model of a battery comprising an impedance circuit for simulating the electrochemical charging and discharging of the battery is also disclosed. A circuit (100) for modeling a lead-acid battery having an RC network for simulating the impedance of cells of the battery is also disclosed. A method of modeling a lead-acid battery with an electrical circuit (100) comprising a charging circuit (111), an electrochemical reaction circuit (113), and a voltage drop circuit (115) is also disclosed. A method for constructing an equivalent electrical circuit model of a lead-acid battery is also disclosed.

Low voltage differential signal driver circuit and method

Abstract: Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.

A delay metric for RC circuits based on the Weibull distribution

Abstract: Physical design optimizations such as placement, interconnect synthesis, floorplanning, and routing require fast and accurate analysis of RC networks. Because of its simple close form and fast evaluation, the Elmore delay metric has been widely adopted. The recently proposed delay metrics PRIMO and H-gamma match the first three circuit moments to the probability density function of a gamma statistical distribution. Although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. As an alternative to matching to the gamma distribution, we propose to match the first two circuit moments to a Weibull distribution. The result is a new delay metric called Weibull based Delay (WED). The primary advantages of WED over PRIMO and H-gamma are its efficiency and ease of implementation. Experiments show that WED is robust and has satisfactory accuracies at both near- and far-end nodes.

Octave tunable, highly linear, RC-ring oscillator with differential fine-coarse tuning, quadrature outputs and amplitude control for fiber optic transceivers

Abstract: This paper presents a low-voltage, RC-ring oscillator for fiber optic transceivers (SDH/SONET applications). It has one octave coarse tuning range, differential tuning inputs, quadrature outputs and a linear fine-control. A replica biasing circuit regulates the common-mode voltage and the amplitude at the output. The oscillator has been realized in a pre-production 70 GHz f/sub T/, SiGe BiCMOS process (QUBIC4G). The tuning range covered with process and temperature variations is 3.4-6.8 GHz. At 6.6 GHz oscillation frequency the measured phase noise is -92 dBc/Hz at 3 MHz; offset from the carrier. The typical power consumption of the VCO core is 80 mW from a 2.5 V power supply and the area is 0.3 mm/sup 2/.

Improved Spice models of aluminum electrolytic capacitors for inverter applications

Abstract: Impedance modeling of aluminum electrolytic capacitors presents a challenge to design engineers, due to the complex nature of the capacitor construction Unlike an electrostatic capacitor, an electrolytic capacitor behaves like a lossy coaxial distributed RC circuit element whose series and distributed resistances are strong functions of temperature and frequency This behavior gives rise to values of capacitance, ESR (effective series resistance), and impedance that vary by several orders of magnitude over the typical frequency and temperature range of power inverter applications Existing public-domain Spice models do not accurately account for this behavior In this paper, a physics-based approach is used to develop an improved impedance model that is interpreted both in pure Spice circuit models and in math functions

350 MHz opamp-RC filter in 0.18 m CMOS

Abstract: A 350 MHz fifth-order elliptic opamp-RC filter demonstrates that opamp-based filters need not have bandwidth disadvantages compared to transconductor-based filters The filter, fabricated in standard digital 018 /spl mu/m CMOS with 18 V V/sub DD/, achieves 05 Vp-p signal swing at -40 dB THD

Analysis of high speed p-i-n photodiode S-parameters by a novel small-signal equivalent circuit model

Abstract: A novel small-signal radio frequency (RF) equivalent-circuit of the side-illuminated input tapered waveguide-integrated p-i-n photodiodes (WG PIN PD) is proposed. The proposed RF equivalent-circuit involves both the carrier-transit effect and the external resistance-capacitance (RC) time constant limitation on the frequency response of the p-i-n PD. The carrier-transit effect is realized by adding an RC circuit to an ideal voltage-controlled current source as the input opto-RF equivalent circuit. The carrier transit-time effect is equivalently represented by the time-constant of this input RC circuit. This new equivalent circuit model fits well with both the measured reflection and optoelectronic conversion parameters of the WG PIN PD in a broad frequency range from 45 MHz to 50 GHz.

Current controlled delay circuit

Abstract: A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

Semiconductor-on-insulator resistor-capacitor circuit

Abstract: A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Abstract: /sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.

A 1-V, self adjusting, 5-MHz CMOS RC-oscillator

Abstract: A 5-MHz, self adjusting CMOS RC-oscillator for portable biomedical applications is presented. The oscillator is capable of operating. with a 1-V power supply and it features low current consumption (20 /spl mu/A @ 1 V) and low sensitivity to supply voltage and temperature variations. The total accuracy of the oscillator is within 5 % with component tolerances of 1 % in external elements R and C. The design was fabricated in a 0.35 /spl mu/m n-well standard digital CMOS process with threshold voltages of 0.5 V and -0.65 V. The design and the operation of the RC-oscillator with measurement results of fabricated chips are presented.

DTT: direct truncation of the transfer function - an alternative to moment matching for tree structured interconnect

Abstract: A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reduced-order transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The method is numerically accurate for any order of approximation, which permits approximations to be determined with a large number of poles appropriate for approximating RLC trees with underdamped responses. The method is computationally efficient with a complexity linearly proportional to the number of branches in an RLC tree. A common set of poles is determined that characterizes the responses at all of the nodes of an RLC tree which further enhances the computational efficiency. Stability is guaranteed by the DTT method for low-order approximations with less than five poles. Such low-order approximations are useful for evaluating monotone responses exhibited by RC circuits.

Output buffer with slew rate control and a selection circuit

Abstract: An output buffer having a controlled output slew rate comprises a first predriver circuit having a first RC circuit and a first output node and a second predriver circuit having a second RC circuit and a second output node. A buffer input node is coupled to the first and second predriver circuits. The output buffer further includes an output circuit having first and second input nodes and a third output node, where the first and second input nodes are coupled, respectively, to the first and second output nodes. The time constants of the RC circuits control a signal slew rate at the third output node of the output circuit, and the value of R may be selected to provide a predetermined, controlled slew rate range at the third output node. A selection circuit aids in the selection of an appropriate value for R.

Explicit transfer function of RC polyphase filter for wireless transceiver analog front-end

Abstract: This paper derives explicit frequency transfer functions for first-, second- and third-order RC polyphase filters (which are important components in analog front-end of wireless transceivers for I, Q signal generation and image rejection) using a concept of complex signal and circulant matrix properties. The results allow us to exploit their characteristics systematically.

Transconductor and filter circuit using the same

Abstract: A filter circuit is provided for suppressing an increase of circuit area, enabling easy circuit design, realizing a reduction of power consumption by a common control voltage operation, and able to stably control the cut-off frequency. The filter circuit includes a differential circuit and a control circuit. The differential circuit includes a first MOS transistor connected to a first current source and a second MOS transistor connected to a second current source. The control circuit controls the out currents of the first and second current source and provides a control signal to the first and second MOS transistors.

Amplifier circuit for adding a laplace transform zero in a linear integrated circuit

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in parallel with one or more of the gain stages in the amplifier. In operation, the capacitance of the second capacitor and an input impedance of the second gain stage of the second circuit introduce a zero in the closed loop feedback system at the third node. The compensation circuit can be applied to a switching regulator controller for adding a zero in the feedback system of a switching regulator.

Rank-order filter design with a sampled-analog multiple-winners-take-all core

Abstract: We propose a sampled-analog rank-order filter (ROF) architecture of complexity O(n/sup 2/). It yields a very compact structure because the devices used are essentially of minimum geometry. Its sole active building block being the simple CMOS inverter, the circuit exhibits an excellent low-voltage compatibility. Furthermore, it can support a rail-to-rail common-mode input range. It is inherently fast due to fully parallel signal processing and speed is expected to increase with technological scaling at the same rate as purely digital circuitry. Finally, it supports full programmability of the rank by means of an analog reference voltage. The ROF is based on a pair of multiple-winners-take-all (mWTA) circuits and a set of AND gates. The paper includes a description of the architecture and a detailed analysis of the mWTA. Most relevant design issues are addressed and experimental results obtained from a fabricated ROF are presented.

Method and apparatus for split reference sampling

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Simulation and Optimization of the Power Distribution Network in VLSI Circuits

Abstract: In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency-domain sensitivity-analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

A thermal model for igbt modules and its implementation in a real time simulator

Abstract: As the power density and switching frequency increase, thermal analysis of power electronics system becomes imperative. The analysis provides valuable information on the semiconductor rating, long-term reliability and efficient heat-sink design. The aim of this thesis is to build a comprehensive thermal model for the power IGBT modules used in three-phase inverters in order to predict the dynamic junction temperature rise under real operating conditions. The thermal model is developed in two steps: first, the losses are calculated and then the junction temperature is estimated. The real-time simulation environment dictates the requirements for the models: easy implementation on the software platform SIMULINK and fast calculation time. The power losses model, which is based on the look-up table method for calculating the conduction and switching losses, are successfully built and implemented in the real time simulation environment. The power losses equations are derived from the experimental data. Several algorithms are developed to catch every switching event and to solve the synchronization problem in a real-time system. An equivalent RC network model is built to perform the thermal analysis. The parameters of the thermal network are extracted from the junction to case and case to ambient dynamic thermal impedance curves. Two separate approaches are followed in deriving these thermal characteristic curves. The first approach uses the experimental data available while the second approach uses the commercial software package ANSYS. The 3-D simulation results using ANSYS agree well with the experimental data and therefore can be relied upon to extract the parameters of the thermal RC network. The latter is successfully implemented using the transfer function method, and is then built in SIMULINK environment for the use in a real time simulator. The power losses and thermal RC network models are extensively tested in a real time simulator environment. The accuracy of the models is confirmed by comparing their predictions with the experimental data.

Integrated FET and driver for use in a synchronous dc-dc conversion circuit

Abstract: An integrated driver circuit includes a low side component and a synchronous dc voltage converter circuit. A sync FET ( 8 ) is controlled by a driver ( 32 ) powered between high and low voltage power connections ( 134, 138 ). A timing circuit ( 150 ) controls the driver circuit in accordance with a signal on a control input. The driver circuit ( 32 ) is isolated from the timing circuit ( 150 ), for example by a level shift circuit ( 136 ) and the low voltage power connection ( 138 ) of the driver circuit is directly connected to the source ( 108 ) of the sync FET ( 8 ). This arrangement is intended to reduce transient voltage effects.

Method and apparatus for near losslessly measuring inductor current

Abstract: The present invention provides a measuring circuit for measuring a current of an inductor with minimum losses and errors According to one embodiment of the invention, the measuring circuit comprises an op-amp (32), a RC network (34) connected in a feedback loop of the op-amp, and a scaling resistor (42) connected in series to one of the input terminals of the op-amp By setting the RC constant of the RC network to be equal to the ratio of the inductor value over its internal resistance value, the inductor current can be derived independent of the frequencies of AC signals

Bias circuit for maintaining a constant value of transconductance divided by load capacitance

Abstract: A bias circuit (126) is described for use in biasing an operational amplifier (110) to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. The bias circuit (126) includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit (136) for developing an equivalent resistance between the current source devices. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operation amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variation. Furthermore, by positioning the resistance equivalent circuit (136) between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations.