Showing papers on "RC circuit published in 2006"

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply

Violation of Kirchhoff's Laws for a Coherent RC Circuit

Abstract: What is the complex impedance of a fully coherent quantum resistance-capacitance (RC) circuit at gigahertz frequencies in which a resistor and a capacitor are connected in series? While Kirchhoff's laws predict addition of capacitor and resistor impedances, we report on observation of a different behavior The resistance, here associated with charge relaxation, differs from the usual transport resistance given by the Landauer formula In particular, for a single-mode conductor, the charge-relaxation resistance is half the resistance quantum, regardless of the transmission of the mode The new mesoscopic effect reported here is relevant for the dynamical regime of all quantum devices

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR

Abstract: In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively

A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers

Abstract: The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer As a drawback, an off-chip component and an additional LNA are introduced, raising costs Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 018-/spl mu/m CMOS solution with outstanding linearity and noise performances The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out Sixty samples from two distinct fabrication lots have been characterized Minimum IIP2 is +78 dBm For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested IIP2 values are always lower Other measured performance results are: 16-dB gain with 45-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV//spl radic/Hz input referred noise voltage density while drawing 4 mA from 18 V

On the development of a compact sub-nanosecond tunable monocycle pulse transmitter for UWB applications

Abstract: Development of a new sub-nanosecond monocycle pulse transmitter with tunable pulse duration for short-range low-power ultra-wideband radar and communication systems is presented along with detailed design and analysis. The developed pulse transmitter is simple, compact, and can be realized using planar or uniplanar integrated circuits. A novel RC coupling circuit along with a high driving current, provided by a high-speed amplifier and buffers, are used to obtain an increase in the output power. A decoupling circuit is implemented to reduce ringing on the monocycle pulse and provide necessary pulse clamping. Tuning of the output monocycle-pulse duration is achieved by using two distributed delay lines, coupled together by the decoupling network, each spatially loaded with antiparallel p-i-n diodes that are alternately switched on and off. Measurement results show tunable monocycle pulse durations in range of 0.4-1.2 ns, approximately corresponding to the operating frequency range of 0.15-3.7 GHz, and 200-400 mW of pulse peak power. The calculated and measured pulse durations also agree reasonably well

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Abstract: Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.

RC-RCD clamp circuit for ringing losses reduction in a flyback converter

Abstract: An RCD clamp circuit is usually used in flyback converters, in order to limit the voltage spikes caused by leakage transformer inductance. Oscillation ringing appears due to the clamp diode, which deteriorates the converter's power rate. This brief describes this ringing phenomenon and the use of an RC-RCD clamp circuit for damping the clamp diode's oscillation. This clamp circuit is capable for improving a flyback converter's power ratio.

Semiconductor integrated circuit for communication

Abstract: The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.

A Method of Transformation from Symbolic Transfer Function to Active- RC Circuit by Admittance Matrix Expansion

Abstract: Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters

Clock and data recovery circuit and method thereof

Abstract: A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between a data signal and a plurality of clock signals to generate two proportional control signal and two integration control signal for respectively controlling the first charge pump and the second charge pump to generate a first current and a second current. The proportional load circuit and the integration load circuit respectively receive the first current and the second current to output a proportional voltage and an integration voltage. The voltage control oscillating circuit adjusts the phase and frequency of the plurality of clock signals in response to the proportional voltage and the integration voltage.

Current sensing in multiple coupled inductors by time constant matching to leakage inductance

Abstract: Voltage regulators often have coupled output inductors because coupled output inductors provide improvements in cost and efficiency. Coupled inductors are often used in multi-phase voltage regulators. Feedback control of voltage regulators often requires accurate and responsive sensing of output current. Provided is a technique for accurately sensing the magnitude of output current in coupled inductors. An RC circuit (comprising a resistor and capacitor in series) is connected in parallel with the coupled inductor. The inductor has a leakage inductance Lk and a DC (ohmic) resistance of DCR. The resistor and capacitor are selected such that an RC time constant is equal to an L/R time constant of Lk/DCR. With the matching time constants, a sum of voltages on the capacitors is accurately proportional to a sum of currents flowing in the output inductors. Also provided is a technique for sensing current when an uncoupled center tap inductor is present.

Zero voltage zero current switching converter

Abstract: A power converter circuit includes an input switching circuit, an isolation circuit, a rectifier circuit that includes a least a pair of rectifiers, and an output circuit. The input switching circuit receives a first voltage and generates an AC voltage. The isolation circuit has a primary side configured to receive the AC voltage from the input switching circuit and a secondary side. The secondary side communicates with the rectifier circuit and the output circuit. The output circuit includes a secondary inductor and a diode. The secondary inductor communicates with a primary inductor and either the rectifier circuit or the secondary side. The diode communicates with the primary inductor, the secondary inductor, and the rectifier circuit. The secondary inductor inhibits current flow through the rectifier circuit and forces current flow through the diode when no voltage is applied to the primary side of the isolation circuit.

Capacitor charging methods and apparatus

Abstract: A capacitor charging circuit is provided with a primary side output voltage sensing circuit including an RC network having an RC time constant with a predetermined relationship to the RC time constant of the output capacitor. Once the capacitor voltage reaches a fully charged level, the charging mode is terminated. The output voltage is continuously detected by measuring the voltage across the primary side RC network that decays at a predetermined rate with respect to the output capacitor and the charging mode is commenced once the RC voltage falls to a predetermined level. According to a further aspect of the invention, a switch control circuit in a flyback converter controls the switch off time in response to detection of a change in the slope polarity of the voltage at a terminal of the switch.

Temperature-compensated inductor DCR dynamic current sensing

Abstract: A resister network having a negative temperature coefficient (NTC) may be utilized to create a temperature compensated equivalent resistance “R” for a current sensing RC network used in measuring inductor current of a DC-to-DC converter or a general switching regulator that needs to use inductor current as a control signal. The NTC resistor of the RC network effectively compensates for the positive temperature coefficient of the switching regulator inductor's inherent DC resistance (DCR). Keeping the time constants of the RC network and the switching regulator inductor substantially matched improves operation of cycle by cycle based control modes such as peak current sensing by the switching regulator controller in performing peak current control for the DC-to-DC converter.

A novel floating lossy inductance realization topology with NICs using current conveyors

Abstract: A negative-impedance converter (NIC) is a useful component in the circuit synthesis theory especially for active RC filter design. In this brief, usefulness of the NIC is shown in a floating inductance realization topology that is an alternative application area for the component. A new floating parallel RL realization topology employing two NICs and three passive components is presented

Design considerations of time constant mismatch problem for inductor DCR current sensing method

Abstract: This paper identifies advantages and disadvantages of several commonly used current sensing methods such as dedicated sense resistor sensing, MOSFET R/sub DS(ON)/ current sensing, and inductor DC resistance (DCR) current sensing. Among these current sense methods, inductor DCR current sense will become dominant one in the future. The mismatching issue between the time constant made by the current sensing RC network and the one formed with output inductor and its DC resistance is addressed. A small signal model of a buck converter using inductor DCR current sensing with mismatched time constants is presented, and the modeling has been verified experimentally.

Capacitive load driving circuit, electrostatic transducer, method of setting circuit constant, ultrasonic speaker, display device, and directional acoustic system

Abstract: A capacitive load driving circuit includes an error amplification circuit that amplifies a difference between an external input signal provided to one input terminal and a negative feedback signal provided from the following negative feed back circuit to the other input terminal; a modulation circuit that pulse-modulates the signal outputted from the error amplification circuit; a power switching circuit that switches between a power supply voltage and a ground potential or between a positive power supply voltage and a negative power supply voltage; a gate driving circuit that generates a gate driving signal for switching-controlling a switching element configuring the power switching circuit, from a modulated signal outputted from the modulation circuit; a low-pass filter that is connected to an output side of the power switching circuit and removes switching carrier components included in an output signal of the power switching circuit; an output transformer that boosts an output signal of the low-pass filter and has a primary winding connected to an output terminal of the low-pass filter; a capacitive load that is connected in parallel with a secondary winding of the output transformer; and a negative feedback circuit that performs a negative feedback from the output terminal of the low-pass filter to an input side of the error amplification circuit.

Gate resistance modeling of multifin MOS devices

Abstract: This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.

Delayed feedback chaotic oscillator with improved spectral characteristics

Abstract: A chaotic oscillator, including a nonlinear unit, an amplifier, an RC filter and a delay line, is described. Depending on the gain the circuit exhibits mono- or two-scroll chaotic oscillations. The two-scroll oscillations, in comparison with the mono-scroll oscillations, are characterised by three times higher fundamental frequency.

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

Abstract: This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

A Low-Cost High-Efficiency CCFL Inverter With New Capacitive Sensing and Control

Abstract: A new low-cost and efficient cold cathode fluorescent lamp (CCFL) inverter for liquid crystal display (LCD) application is suggested in this paper. The topology of the inverter is derived from modified class E-type resonant electronic ballasts and has a dc-like input current. In addition, a new sensing circuit for lamp current and transformer voltage is proposed. A simple RC-network measures the voltage of a ballasting capacitor in series with the lamp instead of the lamp current itself while the lamp is floated. Utilizing the printed circuit board capacitors for the sensing capacitors and integrating small-valued sensing resistors into a control integrated circuit make the inverter very simple, efficient, and cost-effective. The new sensing circuit can solve many problems that arise when a terminal of the lamp is grounded to sense the lamp current. The control circuits for the prototype experiments are also described in detail. The frequency control scheme with a fixed off-time and a varying on-time was chosen to maintain the operation of zero-voltage switching in the entire dimming range and to reduce the complexity of the control circuits. The control circuits have an analog dimming function using a current control loop, a low frequency pulsewidth modulation dimming, open-lamp protection and voltage regulation, and soft-on/off functions

Ring Oscillation Circuit, Delay Time Measuring Circuit, Testing Circuit, Clock Generating Circuit, Image Sensor, Pulse Generating Circuit, Semiconductor Integrated Circuit, and Testing Method Thereof

Abstract: A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator.

A New Extraction Technique for the Complete Small-Signal Equivalent-Circuit Model of InGaP/GaAs HBT Including Base Contact Impedance and AC Current Crowding Effect

Abstract: In this paper, both ac current crowding and base contact impedance are considered and included in the T-type small-signal equivalent circuit of InGaP/GaAs heterojunction bipolar transistors. The ac current crowding effect and base contact impedance are modeled as a parallel RC circuit, respectively. Devices parameters of the equivalent circuit are obtained by a new parameters extraction technique. The technique is to directly analyze the two-port parameters of multibias conditions (cutoff-bias, open-collector, and active-bias modes). The parallel capacitances (CB and Cbi), base resistances (RB and Rbi), and base inductance (LB) are especially determined under the active-bias mode without numerical optimization. In addition, the small-signal equivalent circuits of cutoff-bias and open-collector modes are directly derived from the active-bias mode circuit for consistency. By considering base contact impedance and intrinsic base impedance effects in the presented small-signal equivalent circuit, the calculated S-parameters agree well with the measured S-parameters. The observed difference in the slope for the unilateral power gain (U) versus frequency at high frequency is mainly attributed to the ac emitter current crowding effect and well modeled in this study

Energy consumption in RC tree circuits

Abstract: In this paper, resistance-capacitance (RC) tree networks are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an equivalent time constant is analytically derived from an exact analysis for very slow and very fast input transitions. The model is then extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. The approach is completely analytical and leads to closed-form results. Analytical results are explicitly derived for different inputs, such as the ramp and the exponential waveforms which are usually encountered in current VLSI circuits, as well as the saturated sine input. Due to its simplicity, the proposed energy expression is suitable for pencil-and-paper evaluation and allows for an intuitive understanding of the network dissipation. The energy expression proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations.

Driving circuit and electronic device using the same

Abstract: A driving circuit is disclosed that has low power consumption and supplies a current to a load. The driving circuit includes a constant current circuit section to generate and output a predetermined constant current, a current mirror circuit section to generate a current proportional to an input current supplied from the constant current circuit section and supply the current to the load, and a constant voltage supplying circuit section to generate a constant voltage and supply the constant voltage to a series circuit of the load and an output transistor of the current mirror circuit. The constant voltage supplying circuit section gene-rates the constant voltage so that an output voltage of the current mirror circuit section equals an input voltage of the current mirror circuit section.

Startup circuit and startup method for bandgap voltage generator

Abstract: A startup circuit for activating a bandgap circuit is provided, including a switching circuit, an activating circuit, and a controlling circuit. The controlling circuit is used for monitoring and comparing two voltages to determine whether the switching circuit should be turned on so as to activate the bandgap circuit. One of the two voltages that are monitored is a zero temperature coefficient voltage, and the other of the two voltages that are monitored is a negative temperature coefficient voltage.

Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology

Abstract: The dominant mechanisms are analyzed of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology. Data reliability under transient irradiation is discussed in relation to photocurrents, rail-span collapse, and the circuit and layout design of memory cells. The response is simulated of SOS integrated resistors to transient radiation. Optimal parameter values are thus determined for the resistor used in the RC network of a memory cell. It is found that the data reliability of the memory circuits considered is affected by the cross coupling of memory cells sharing a read/write line. The lifetime of radiation-induced charge carriers is estimated by experiment and computer simulation.

Resistor/capacitor based identification detection

Abstract: A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Piezoelectric oscillation circuit

Abstract: A piezoelectric oscillation circuit includes: a DC power supply; a stabilized power supply that stabilizes a voltage variation in a DC voltage supplied from the DC power supply; an oscillation circuit unit that uses a piezoelectric vibrator as a vibratory source; a buffer circuit unit to which an output signal output from the oscillation circuit unit is input, a plurality of stages of inverter circuits are connected in series, and a depletion type MOS transistor is connected to the last stage inverter circuit; an output amplification circuit that amplifies an output of the buffer circuit; an output level adjustment circuit that includes a plurality of MOS switches and resistive elements and adjusts an output level by varying a gate voltage of an Nch-transistor included in the output amplification circuit; a memory circuit that stores data for selecting one of the plurality of MOS switches; and a decoder that generates an analog signal to be input to the MOS switch on the basis of the data stored in the memory circuit.

RC oscillator integrated circuit including capacitor

Abstract: An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1/N-times division of the received current signal according to an input clock signal, and generating a 1/N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.