Showing papers on "RC circuit published in 2008"

Comparison of ultracapacitor electric circuit models

Abstract: Due to ultracapacitorspsila unique features, the electrical performances and reliabilities of electrical systems using ultracapacitors can be improved. It is important to have a good ultracapacitor model for simulation and assisting electrical system design and product development. Several kinds of ultracapacitor models are given these years. Especially, electric circuit models are the interested ones for electrical engineers. This paper concentrates on the electric circuit model. Three basic RC network models are discussed in detail, including modeling ideas, circuit formation, linear/nonlinear factors and evaluations of each model. The general electric circuit model considering the inductance and leakage current effects are given. Model selection depends on the specific applications of ultracapacitor. Based on the analysis in this paper, recommendations of ultracapacitor selection strategies are provided.

A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications

Abstract: We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.

Bandwidth enhancement for a touch sensor panel

Abstract: A system is disclosed for enhancing the stimulation signal bandwidth for a touch sensor panel and maintaining relatively uniform touch sensitivity over the touch sensor panel surface. In one embodiment, a bandwidth enhancement circuit is coupled in parallel to a sensor circuit. The sensor circuit includes a source of stimulating voltage, a drive line, a sense line, and a charge amplifier. The drive line and the sense line are coupled with each other by a mutual capacitance Csig. The bandwidth enhancement circuit can be a RC circuit coupled in parallel to the sensor circuit. The bandwidth enhancement circuit can be represented by two serially coupled resistors, each of which is also coupled to ground on one end, and two capacitors. In particular, one of the capacitors couples the bandwidth enhancement circuit to the drive line, and the other capacitor couples the bandwidth enhancement circuit to the sense line.

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

Abstract: This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 7-1, the recovered clock jitter is 0.3 psrms and 4.3 pspp. The retimed data exhibits 500 mV pp output swing and 9.6 pspp jitter with BER <10-12. Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.

Direct interface circuit to linearise resistive sensor bridges

Abstract: This paper proposes the direct connection of different configurations of resistive sensor bridges to a microcontroller without any intermediate active component. Such a direct interface circuit relies on measuring the discharging time of a RC network that includes the resistances of the sensor bridge. For quarter-, half-, and full-bridge circuits, we combine the discharging times to estimate the fractional resistance change x of the bridge arms. Experimental results for half- and full-bridge circuits emulated by resistors yield a nonlinearity error below 0.3%FSR (full-scale range) for x between 0 and 0.1 and an effective resolution of 11 bit. Measurements on two commercial magnetoresistive sensors yield higher nonlinearity errors: 1.8%FSR for an AMR (Anisotropic Magnetoresistive) sensor and 5.8%FSR for a GMR (Giant Magnetoresistive) sensor, which are mainly due to the nonlinearity of the sensors themselves. Therefore, the nonlinearity of the measurement is limited by the sensors, not by the proposed interface circuit and linearisation algorithm.

Accurate Systematic Model-Parameter Extraction for On-Chip Spiral Inductors

Abstract: A systematic model-parameter-extraction technique is presented for accurately modeling on-chip spiral inductors in radio frequency integrated circuits (RFICs). The model is a pi-circuit with an additional parallel RC network connecting both vertical branches to account for substrate coupling. The extraction starts with extracting the series inductance and resistance at low frequencies. Then, the oxide capacitance is evaluated in an intermediate frequency range. Afterward, the substrate effects including the substrate resistance and capacitance, as well as coupling, are extracted at higher frequencies. All the lumped circuit element values are analytically determined by the network analysis from the measured network parameters (S- or Y-parameters). The proposed approach thus can provide better circuital interpretations of the inductor behaviors for facilitating the design of RFIC inductors. Square and circular CMOS spiral and octagonal BiCMOS7 spiral inductors are investigated to test this technique. Highly accurate frequency responses by the extracted parameters are obtained over a wide frequency band without any optimization. This reveals the validation and capability of the proposed parameter-extraction method.

Method for faulty orientation and subsection of power system low current grounding

Abstract: An indication and sectionalizing method of the small current grounding fault of the power system relates to the detecting field of the grounding fault of the power system. The method is characterized in that the back zero sequence equivalent capacity of the detecting point is estimated, simultaneously the related information of the transient phase voltage and the transient zero sequence current caused by the fault is utilized as the basis of the fault indication and sectionalizing. The back zero sequence equivalent capacity of the detecting point is estimated according to the collected transient phase voltage and the transient zero sequence current after the fault, and whether the fault detecting device is actuated to alarm is determined according the value of the zero sequence capacitor.The method has the advantages of only need of one phase voltage transformer for realization, effective decrease of the production cost, obtaining the phase voltage signal for the cable line via the sheet iron that is covered on the line and grounded via the RC circuit, being simple and feasible, higher amplitude of the transient signal than that of the stationary signal and easy detecting, and noinfluence from the grounding mode of the neutral point of the system.

Methods and apparatus for current sensing

Abstract: Methods and apparatus for current sensing according to various aspects of the present invention sense the current in a circuit, such as an inductor circuit. The current sensing systems may comprise an RC element connected such that the RC time constant matches the L/R time constant of the inductor. The current sensor may be configured to generate voltages that are proportional to the instantaneous current in the inductor with scaled gain for a wide range of inductor self resistance (DCR) values.

Spread spectrum control pll circuit and its start-up method

Abstract: A calibration circuit ( 19 ) adjusts at least one of one of a charging current of a charge pump circuit ( 12 ) and a capacitance value of a filter capacitor in a loop filter circuit ( 13 ) and a gain of a voltage controlled oscillator ( 14 ), depending on a frequency of a reference clock signal input to a calibration circuit ( 10 ).

Characterization and Modeling of the Voltage Dependency of Capacitance and Impedance Frequency Characteristics of Packed EDLCs

Abstract: Frequency characteristics and their dependence on charge voltage for a packed electric double layer capacitor (EDLC), which consists of a series of connected EDLC cells, are characterized and modeled based on small ac signal analysis. The results indicate that rated capacitance of a packed EDLC is valid only at frequencies lower than 0.01 Hz at the rated charge voltage but the capacitance is lower for frequencies higher than 0.01 Hz and for lower charge voltages. A conventional simple RC-equivalent circuit, consisting of a capacitor and a resistance in series, is inadequate for expressing EDLC frequency characteristics; therefore, a second-order RC equivalent circuit is used as a model for a packed EDLC. The charge voltage dependency in the frequency characteristics of packed EDLC is evaluated, based on this equivalent circuit. The parameters of the equivalent circuit and their charge voltage dependencies are evaluated from the results. The proposed packed EDLC model is validated by charge and discharge operations in an experimental circuit. The results show that the model can accurately assess the charge stored in a packed EDLC.

A 1.2-V CMOS $RC$ Oscillator for Capacitive and Resistive Sensor Applications

Abstract: An accurate self-adjusting CMOS RC oscillator for capacitive and resistive sensor applications has been designed and manufactured. The oscillator operates with supply voltages from 1.2 to 3 V and achieves an internal accuracy of plusmn0.7% with a temperature range from -20degC to 60degC. The RC oscillator was fabricated in a 0.35-mum standard n-well CMOS process with threshold voltages of 0.5 and -0.65 V. Its design and operation are described, and results of measurements performed on the fabricated chips are presented.

A 46-ppm/°C temperature and process compensated current reference with on-chip threshold voltage monitoring circuit

Abstract: A CMOS current reference circuit has been developed in 0.35-mum CMOS process. The circuit consists of a voltage reference circuit, a noninverting amplifier, and an output MOS transistor. The circuit generates a reference current independent of temperature and process variations. Temperature- and process-compensation were achieved by utilizing the zero temperature coefficient bias point of a MOSFET. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference current of 18.4 muA on average. The temperature coefficient, load sensitivity, and process sensitivity (sigma/mu) of the circuit were 46-ppm/sigmaC, 1.5%/V, and 4.4%, respectively. The circuit can be used as a current reference circuit for high precision analog circuit systems.

High voltage esd protection featuring pnp bipolar junction transistor

Abstract: A protection circuit is disclosed that protects a semiconductor device from damage due to an electrostatic discharge. One such protection circuit comprises a vertical pnp hetero- junction bipolar transistor (HBT) (350) connected between terminals such as supply terminals of the device, configured to conduct during an electrostatic discharge. The protection circuit also comprises a trigger circuit, such as a transient activated RC circuit connected between the terminals to detect the electrostatic discharge and control the transistor based on the detected electrostatic discharge. A Darlington transistor pair in the trigger circuit can be used to multiply the effective capacitance and HBT drive current. The HBT transistor absorbs energy from the electrostatic discharge and clamps the over- voltage across the terminals. The protection circuit may also be used across other VO terminals of the device.

Electrostatic discharge circuit and method

Abstract: A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive.

Dynamic Thermal Analysis of High-Power LEDs at Pulse Conditions

Abstract: In this letter, the thermal evaluation of high-power LED packages at pulse conditions was reported. A theoretical calculation model was proposed based on the analogy between the thermal and electrical RC circuits. The thermal performance of LED packages driven by pulse input was calculated using the RC network extracted from transient thermal measurement. The junction temperature fluctuation band decreases with the frequency at certain duty cycles. The saturated average junction temperature rise linearly increases with the duty cycle at certain frequencies. These predictions were verified by the real-time junction temperature measurement using the peak shift method at pulse conditions. The theoretical model was found to be effective and applicable to the evaluation of the thermal performance of LEDs working at pulse conditions.

ESD detection circuit and related method thereof

Abstract: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.

Light-adjusting and current-limiting control circuit

Abstract: A light-adjusting and current-limiting control circuit for a lamp includes a sampling circuit formed of a manganese-copper line or a current transformer, a power circuit provided with resistors, capacitors, diodes, a Varistor and a zener diode, a signal adjusting circuit composed of diodes, resistors, a varistor, triacs and capacitors, and a control output circuit having a thyristor, diodes, a relay and an LED. The control output circuit can be replaced with a light-adjusting input circuit, a chip processor control circuit, a zero-crossing detection circuit and a two-way silicon controlled rectifier control output circuit 5. Thus, the invention has a low cost, a small size and an excellent precision, compared to conventional ones.

Power management circuit and method of frequency compensation thereof

Abstract: A power management circuit includes a regulator circuit, a first frequency compensation circuit, a first switch circuit and a detection circuit. The regulator circuit includes a signal output end. The first switch circuit is turned on in response to an enabled first control signal such that the first frequency compensation circuit is coupled to the regulator circuit. The detection circuit determines whether an output capacitor is coupled to the signal output end, and generates the enabled first control signal to turn on the first switch circuit and connect the first frequency compensation circuit to the regulator circuit when the output capacitor is not coupled to the signal output end. Therefore, the regulator circuit is frequency compensated by the first frequency compensation circuit.

AC and DC temperature compensation scheme for DCR current sense

Abstract: A current sensing circuit with AC and DC temperature compensation for sensing current through an output inductor which has an inherent DC resistor with a temperature varying resistance. A first RC circuit is coupled across the output inductor and has a time constant. The first amplifier provides a sense signal indicative of voltage of the first RC circuit. The second RC circuit is coupled to a first correction node and receives the sense signal. The second resistor has a temperature varying resistance so that the second RC circuit has a time constant commensurate with a time constant of the output inductor. The third RC circuit is coupled to a second correction node and has a time constant equal commensurate with the first RC circuit. The second amplifier provides a corrected sense signal based on the correction nodes.

Methods and apparatus for implementing an output circuit

Abstract: An output circuit providing an adjustable output amplitude and common-mode voltage is described. The output circuit includes at least one driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit may also include a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit may be coupled to receive a second bias and to provide an output coupled to the at least one driver circuit and the common-mode feedback circuit.

Digital current sense

Abstract: A circuit for measuring a current in an output inductor of at least one switching power supply having high- and low-side switches connected at a switching node, the output inductor having input and output terminals, the input terminal being connected to the switching node. The circuit including a sensing circuit for detecting a direction of current through the inductor, the sensing circuit generating a sense voltage related to the direction of current; a comparator circuit having an output terminal and input terminals coupled to the sensing circuit and receiving the sense voltage, the comparator circuit providing a comparison output of the sense voltage and an output voltage of the output inductor; and a switched current source circuit controlled by the comparison output for providing a reference current to the sensing circuit, the comparison output turning the switched current source circuit ON and OFF depending on the comparison output and having a duty cycle, whereby the average current flowing through the switched current source circuit is substantially equal to the average current in the sensing circuit and proportional to the duty cycle, the duty cycle being proportional to the inductor current.

A JFET-CMOS Fast Preamplifier for Segmented Germanium Detectors

Abstract: A JFET-CMOS fast charge-sensitive preamplifier for germanium detectors, able to operate at cryogenic temperatures, has been designed, realized, and characterized. The monolithic part of the circuit is realized in a mature 5 V 0.8 m Si CMOS technology, which yields better performances than scaled technologies in this case. The input transistor is an external Si JFET, which can be easily replaced if necessary. The charge-to-voltage gain and the fall-time are as well set through an external RC network. The circuit works in the wide temperature range of 196 to 55 C and is able to drive a terminated coaxial cable with an exceptionally fast and clean transition. Namely, with a detector capacitance of 16 pF and a negative power supply of 3 V it is able to provide a 2.4 V pulse onto a 100 load in less than 13 ns with no ringing. The static power consumption is 8 mW excluding the JFET. The area occupancy of the integrated circuit is as little as 366275 . The noise performance with a 16 pF detector capacitance is 110 r.m.s. electrons both at room temperature and at C, at a quasi-Gaussian shaping time of 10 s. The obtained performance is adequate for gamma-ray spectroscopy and pulse-shape analysis with bulky HPGe segmented detectors.

Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques

Abstract: In this paper, an in-depth analysis of switched-resistor (S-R) techniques for implementing low-voltage low-distortion tunable active-RC filters is presented. The S-R techniques make use of switch(es) with duty-cycle-controlled clock(s) to achieve tunability of the effective resistance and, hence, the RC time constant. The characteristics of two S-R networks utilizing one set (S-1R) and two sets (S-2R) of switch and resistor combinations are analyzed. It will be shown that the S-2R network outperforms the S-1R counterpart in terms of finite-slew-rate-induced distortion, frequency translation, and noise performance. In order to extend the tuning range, an S-R bank scheme is also described. The theoretical analysis was verified by an experiment on a 100-kHz first-order S-R filter prototype, implemented using discrete elements, where several advantages of the S-2R over the S-1R networks are demonstrated. Simulations of 10-MHz low-pass filters based on the S-1R and S-2R techniques in a standard 0.18- mum CMOS process are also included for performance comparison in practical on-chip filter implementations.

Magnetic sensor circuit

Abstract: A magnetic sensor circuit is provided in which an offset of the magnetic sensor circuit can be eliminated to detect a weak magnetic field with high precision. A reference voltage source is provided to charge an input capacitor of a comparator included in the magnetic sensor circuit to a predetermined voltage.

Capacitive sensor and proximity detector using it

Abstract: A capacitive sensor may be used as a proximity detector in an obstruction warning system for road vehicles, e.g. for use when the vehicle is reversing. A digital signal processor 11 sends a sine wave through a sensor RC circuit 1, 7. A sensor plate 3 acts as one plate of a sensor capacitor 1 and the obstruction 45 acts as the other plate 5. Changes in the distance between the car 43 and the obstruction 45 result in changes in the capacitance of the sensor capacitor 1, changing the amplitude and phase of the sine wave output by the sensor RC circuit 1, 7. A reference sine wave, generated by a reference signal circuit 17, 19, 21 is subtracted from the sensor output signal in a subtractor 15. The reference signal has a phase offset from the sensor signal so that the amplitude of the difference signal is highly sensitive to changes in phase of the sensor signal. An additional signal, substantially identical to the sensor signal, is coupled to the output of the sensor RC circuit by a coupling capacitor 41. This provides a path to ground for high frequency noise without disrupting the sensor signal.

Coordinated power sequencing to limit inrush currents and ensure optimum filtering

Abstract: A regulated power supply apparatus and method is provided. A converter circuit is configured to generate a regulated voltage signal from an unregulated voltage signal. A power sequencing circuit includes an unregulated voltage source input terminal and is configured for coupling an unregulated voltage signal to an unregulated voltage signal input terminal of the converter circuit. The power sequencing circuit includes an enable output coupled to the enable signal input terminal and includes a power limiting circuit and a trigger circuit. The power limiting circuit includes a first cascade of discrete analog components as controls for a first switching element and the trigger circuit includes a second cascade of discrete analog components as controls for a second switching element. The first cascade is configured as a charge control circuit for controlling a rate of charge of a first filter network and includes a zener diode coupled in parallel. The second cascade is configured as a detector of voltage levels and generates the enable signal. The first and second switching elements are semiconductor switches. The first filter network is coupled upstream of the converter circuit and a second filter network is coupled downstream. In an exemplary embodiment, the converter circuit is a DC to DC bus converter circuit and the regulated power supply apparatus is a fan controller circuit.

Cascode current mirror circuit, bandgap circuit, reference voltage circuit having the cascode current mirror circuit and the bandgap circuit, and voltage stabilizing/regulating circuit having the reference voltage circuit

Abstract: A cascode current mirror circuit and a bandgap circuit are provided. The circuits are used together and function as a reference voltage circuit. The reference voltage circuit outputs a reference current resistant to temperature variation and ripple-voltage. Accordingly, a voltage stabilizing/regulating circuit corrects error voltage precisely and promptly, and the resultant voltage is temperature insensitive and ripple-voltage-independent.

Phase locked loop

Abstract: A disclosed exemplary embodiment is a phase locked loop comprising a main charge pump driven by a phase error signal, and providing a first input to a loop filter An auxiliary charge pump driven by the phase error signal feeds a second input of the loop filter The loop filter can be an active loop filter comprising an operational amplifier and a feedback RC network The first input of the active loop filter can be an inverting input of the operational amplifier and the second input can be a non-inverting input of the operational amplifier An on-chip stabilizing capacitor fed by the auxiliary charge pump and coupled to the second input of the loop filter is significantly smaller than the conventional stabilizing capacitors The loop filter outputs a regulating voltage for regulating the oscillation frequency of a voltage controlled oscillator in the phase locked loop

Single supply level shifter circuit for multi-voltage designs, capable of up/down shifting

Abstract: A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.