Showing papers on "RC circuit published in 2011"

Applicability of Metal/Insulator/Metal (MIM) Diodes to Solar Rectennas

Abstract: The current-voltage (I-V) characteristics of metal/insulator/metal (MIM) diodes illuminated at optical frequencies are modeled using a semiclassical approach that accounts for the photon energy of the radiation. Instead of classical small-signal rectification, in which a continuous span of the dc I-V curve is sampled during rectification, at optical frequencies, the radiation samples the dc I-V curve at discrete voltage steps separated by the photon energy (divided by the electronic charge). As a result, the diode resistance and responsivity differ from their classical values. At optical frequencies, a diode with even a moderate forward-to-reverse current asymmetry exhibits high quantum efficiency. An analysis is carried out to determine the requirements imposed by the operating frequency on the circuit parameters of antenna-coupled diode rectifiers, which are also called rectennas. Diodes with low resistance and capacitance are required for the RC time constant of the rectenna to be smaller than the reciprocal of the operating frequency and to couple energy efficiently from the antenna. Existing MIM diodes do not meet the requirements to operate efficiently at visible-to-near-infrared wavelengths.

Design of Time-Delay Chaotic Electronic Circuits

Abstract: This paper investigates the problem of the design and the implementation of time-delay chaotic circuits. A simple feedback scheme consisting of a nonlinearity, a first-order RC circuit and a delay block has been fixed and a procedure to design the characteristics of these blocks in order to obtain chaotic dynamics has been introduced. A series of n Bessel filters in cascade is used to implement the time-delay. The suitability of the approach is demonstrated with an example: a new chaotic circuit has been first designed and, then, implemented with off-the-shelf discrete components. The approach allows us to design and implement a new class of time-delay chaotic circuits with simple components, like resistors, capacitors, and operational amplifiers.

Active-RC Filters Using the Gm-Assisted OTA-RC Technique

Abstract: The linearity of conventional active-RC filters is limited by the operational transconductance amplifiers (OTAs) used in the integrators. Transconductance-capacitance (Gm-C) filters are fast and can be linear- however, they are sensitive to parasitic capacitances. We explore the Gm-assisted OTA-RC technique, which is a way of combining Gm-C and active-RC integrators in a manner that enhances the linearity and speed of the latter, while adding negligible extra noise or power dissipation. Measurements from a fifth-order Chebyshev filter with 20 MHz bandwidth, designed in a 0.18 μ m CMOS process, demonstrate the efficacy of Gm-assistance in an active-RC integrator.

Introduction to Circuit Analysis and Design

Abstract: Preface 1 Introduction 11 Electric Circuits 12 How to Study This Book 13 Dimensions and Units 14 Symbols and Notation 15 Symbols Versus Numbers 16 Presentation of Calculations 17 Approximations 18 Precision and Tolerance 19 Engineering Notation 110 Problems 2 Current, Voltage, and Resistance 21 Charge and Current 22 Electric Field 23 Electric Potential and Voltage 24 Ohm's Law and Resistance 25 Resistivity 26 Conductance and Conductivity 27 Resistors 28 E Series, Tolerance, and Standard Resistance Values 29 Resistor Marking 210 Variation of Resistivity and Resistance with Temperature 211 American Wire Gauge (AWG) and Metric Wire Gauge (MWG) 212 DC and AC 213 Skin Effect and Proximity Effect 214 Concluding Remark 215 Problems 3 Circuit Elements, Circuit Diagrams, and Kirchhoff's Laws 31 Schematics and Circuit Diagrams 32 Conductors and Connections 33 Annotating Circuit Diagrams 34 Series and Parallel Connections 35 Open Circuits and Short Circuits 36 Basic Circuit Elements: Resistors and Independent Sources 37 Kirchhoff's Current Law and Node Analysis 38 Kirchhoff's Voltage Law and Mesh Analysis 39 Voltage and Current Dividers 310 Superposition 311 Problems 4 Equivalent Circuits 41 Terminal Characteristics 42 Equivalent Circuits 43 Source Transformations 44 The'venin and Norton Equivalent Circuits 45 Notation: Constant and Time-Varying Current and Voltage 46 Significance of Terminal Characteristics and Equivalence 47 Problems 5 Work and Power 51 Instantaneous Power and the Passive Sign Convention 52 Instantaneous Power Dissipated by a Resistor: Joule's Law 53 Conservation of Power 54 Peak Power 55 Available Power 56 Time Averages 57 Average Power 58 Root Mean Squared (RMS) Amplitude of a Current or Voltage 59 Average Power Dissipated in a Resistive Load 510 Summary: Power Relations 511 Notation 512 Measurement of RMS Amplitude 513 Dissipation Derating 514 Power Dissipation in Physical Components and Circuits 515 Active and Passive Devices, Loads, and Circuits 516 Power Transfer and Power Transfer Efficiency 517 Superposition of Power 518 Problems 6 Dependent Sources and Unilateral Two-Port Circuits 61 Input Resistance and Output Resistance 62 Dependent Sources 63 Linear Two-Port Models 64 Two-Ports in Cascade 65 Voltage, Current, and Power Transfer 66 Transfer Characteristics, Transfer Ratios, and Gain 67 Power Gain 68 Gains and Relative Values in Decibels (dB) 69 Design Considerations 610 Problems 7 Operational Amplifiers I 71 Operational Amplifier Terminals and Voltage Reference 72 DC Circuit Model for an Op Amp 73 The Ideal Op Amp and Some Basic Op-Amp Circuits at DC 74 Feedback and Stability of Op-Amp Circuits 75 Input Resistance and Output Resistance of Op-Amp Circuits 76 Properties of Common Op-Amp Circuits 77 Op Amp Structure and Properties 78 Output Current Limit 79 Input Offset Voltage 710 Input Bias Currents 711 Power Dissipation in Op Amps and Op-Amp Circuits 712 Design Considerations 713 Problems 8 Capacitance 81 Capacitance 82 Capacitors 83 Terminal Characteristics of an Ideal Capacitor 84 Charge-Discharge Time Constant 85 Capacitors in Series and Parallel 86 Leakage Resistance 87 Stray and Parasitic Capacitance Capacitive Coupling 88 Variation of Capacitance with Temperature 89 Energy Storage and Power Dissipation in a Capacitor 810 Applications 811 Problems 9 Inductance 91 Magnetic Field 92 Self Inductance 93 Inductance of Air-Core Coils 94 Inductors 95 Terminal Characteristic of an Inductor 96 Time Constant 97 Inductors in Series and Parallel 98 Energy Storage and Power dissipation in an Inductor 99 Parasitic Self-Inductance 910 Reducing Ripple 911 Inductive Kick 912 Magnetically Coupled Coils and Mutual Inductance 913 Parasitic Mutual Inductance 914 Transformers 915 Ideal Transformers 916 Applications of Transformers 917 Concluding Remarks 918 Problems 10 Complex Arithmetic and Algebra 101 Complex Numbers 102 Complex Arithmetic 103 Conjugate of a Complex Number 104 Magnitude of a Complex Number 105 Arithmetic in a Complex Plane 106 Polar Form of a Complex Number 107 Eulers Identity and Polar Arithmetic 108 The Symbols and 109 Problems 11 Transient Analysis 111 Unit Step Function 112 Notation 113 Initial Conditions 114 First-Order Circuits 115 Second-Order Circuits 116 Time Invariance, Superposition, and Pulse Response 117 Operator Notation 118 Problems 12 Sinusoids, Phasors, and Impedance 121 Sinusoidal Voltages and Currents 122 Time Origin, Phase Reference, and Initial Phase 123 Phasors 124 Phasor Diagrams 125 Impedance and Generalized Ohm's Law 126 Admittance 127 Impedance and Admittance Ratios in dB 128 A Fundamental Relation 129 Circuit Reduction: Elements in Series and Parallel 1210 Time Domain and Frequency Domain 1211 Sinusoidal and DC Steady State 1212 Frequency-Domain Circuit Analysis 1213 Reactance and Effective Resistance 1214 Susceptance and Effective Conductance 1215 Impedance and Admittance Triangles 1216 Linearity and Superposition 1217 The'venin and Norton Equivalent Circuits: Source Transformations 1218 Checking Your Work 1219 Resonance 1220 Quality Factors and Common Resonant Configurations 1221 Simulating Inductance Using Active RC Circuits 1222 Circuit Elements and Physical Circuit Components 1223 Problems 13 Complex Power 131 Definition of Complex Power 132 Notation 133 Power Calculations 134 Reactive Power and Apparent Power 135 Conservation of Complex Power 136 Power Relations in Resonant Circuits 137 Power Factor 138 Power Triangle and Power-Factor Correction 139 Superposition of Complex Power 1310 Power Transfer 1311 Impedance Matching 1312 Problems 14 Three-Phase Circuits 141 Three-Phase Sources 142 Power Transmission and Distribution 143 Residential Wiring 144 Three-Phase Loads 145 Balanced Y-DELTA and DELTA-Y Transformations 146 Power Calculations for Balanced Three-Phase Loads 147 Power-Factor Correction for Three-Phase Loads 148 Instantaneous Power Delivered to a Balanced Load 149 Problems 15 Transfer Functions and Frequency-Domain Analysis 151 Transfer Functions 152 Dependence of a Transfer Function upon Source and Load 153 Gain and Phase Shift 154 Gain in Decibels (dB) 155 Standard Form of a Transfer Function 156 Asymptotic Gain Plots: Linear Factors 157 Asymptotic Gain Plots: Quadratic Factors 158 Asymptotic Plots of Phase Shift Versus Frequency 159 Filters and Bandwidth 1510 Frequency Response 1511 Problems 16 Fourier Series 161 Amplitude-Phase Series 162 Exponential Series and Fourier Coefficients 163 Quadrature Series 164 Summary: Three Forms of Fourier Series 165 Integral Formula for Fourier Coefficients 166 A Table of Fourier Coefficients 167 Modified Fourier Coefficients for Composite Waveforms 168 Convergence of Fourier Series 169 Gibbs' Phenomenon 1610 Circuit Response to Periodic Excitation 1611 Spectra and Spectral Analysis 1612 Problems 17 Operational Amplifiers II: AC Model and Applications 171 AC Model for an Op Amp 172 Linear Resistive-Feedback Amplifiers 173 Linear Reactive-Feedback Circuits 174 Output Swing 175 Slew Rate 176 Amplifiers in Cascade 177 Capacitance Coupling 178 Input Bias Current Compensation in Capacitance-Coupled Amplifiers 179 Power Dissipation in Op Amps and Op-Amp Circuits 1710 Power-Conversion Efficiency 1711 Op-Amp Amplifier Circuit Design 1712 Problems 18 Laplace Transformation and s-Domain Circuit Analysis 181 Definition of the Laplace Transformation 182 Convergence and Uniqueness 183 One-Sided Laplace Transforms 184 Shorthand Notation 185 The Delta Function (Unit Impulse) 186 Tables of Operational Properties and Transform Pairs 187 Inverse Transforms Using Partial-Fraction Expansions 188 Terminal Characteristics and Equivalent Circuits 189 Circuit Analysis in the s Domain 1810 Checking Your Work 1811 s-Domain Transfer Functions 1812 Forced Response and Unforced Response 1813 Impulse Response and Step Response 1814 Relation of s-Domain to Frequency-Domain Transfer Functions 1815 s-Domain Models for Op Amps and Basic Op-Amp Circuits 1816 Circuits in Cascade 1817 Poles, Zeros, and Pole-Zero Plots 1818 Stability 1819 Pole-Zero Cancellation 1820 Dominant Poles 1821 Pole-Zero Plots and Bode Plots 1822 Problems 19 Active Filters 191 Gain 192 Group Delay 193 A Simple Two-Pole Active Filter 194 Sallen-Key (VCVS) Filters 195 State-Variable Biquadratic Filter 196 Modern Filter Design 197 Problems Appendix: Answers to Exercises Index

Lyapunov Balancing for Passivity-Preserving Model Reduction of RC Circuits ∗

Abstract: We apply a Lyapunov-based balanced truncation model reduction method to differential-algebraic equations arising in modeling of RC circuits. This method is based on diagonalizing the solution of one projected Lyapunov equation. It is shown that this method preserves passivity and delivers an error bound. By making use of the special structure of circuit equations, we can reduce the numerical effort for balanced truncation drastically.

Mode Switching RC Network

Abstract: Various embodiments include apparatus, systems, and methods having a conductive contact configured to couple to a resistor-capacitor (RC) network, a device unit coupled to the conductive contact, and a mode switching unit to change a characteristic of a signal at the conductive contact based at least in part on an RC time constant of the RC network. The mode switching unit may switch the device unit between a first operating mode and a second operating mode based on a signal level of the signal.

SparseRC: Sparsity Preserving Model Reduction for RC Circuits With Many Terminals

Abstract: A novel model order reduction (MOR) method, SparseRC, for multiterminal RC circuits is proposed. Specifically tailored to systems with many terminals, SparseRC employs graph-partitioning and fill-in reducing orderings to improve sparsity during model reduction, while maintaining accuracy via moment matching. The reduced models are easily converted to their circuit representation. These contain much fewer nodes and circuit elements than otherwise obtained with conventional MOR techniques, allowing faster simulations at little accuracy loss.

Light source lighting device and luminaire

Abstract: A power supply circuit drives circuits having different numbers of series-connected LEDs without changing a circuit constant or a component. An LED series circuit is connected to a power converter circuit of a power supply circuit. The power converter circuit is controlled by a control arithmetic circuit, and supplies a constant current to the LED series circuit. A voltage detection circuit detects a voltage applied to the LED series circuit. The control arithmetic circuit checks whether the LED series circuit has 40 LEDs or 20 LEDs, based on the voltage detected by the voltage detection circuit. The control arithmetic circuit holds a constant-current value table for 40 LEDs and a constant-current value table for 20 LEDs. In accordance with the detected voltage, the control arithmetic circuit selects one constant-current value table, and controls the power converter circuit based on the constant-current value table selected.

SparseRC : sparsity preserving model reduction for RC circuits with many terminals

Abstract: A novel model order reduction (MOR) method for multi-terminal RC circuits is proposed: SparseRC. Specifically tailored to systems with many terminals, SparseRC employs graph-partitioning and fill-in reducing orderings to improve sparsity during model reduction, while maintaining accuracy via moment matching. The reduced models are easily converted to their circuit representation. These contain much fewer nodes and circuit elements than otherwise obtained with conventional MOR techniques, allowing faster simulations at little accuracy loss.

Embedded Z-source inverter with switched inductor

Abstract: The Z-source inverter has a unique impedance network which can boost up the input voltage and protect against a short circuit. However, the conventional Z-source inverter has disadvantages which are low boost factor, the voltage stress for the Z-source capacitors, and the discrete input current. This paper proposes a circuit which has the switched inductor and embeds the input voltage sources in the Z-source impedance network. The proposed circuit has high boost ratio, reduces the capacitor voltage stress, and realizes the low ripple input current. The operation of the proposed circuit has been confirmed by circuit experiments.

Led drive circuit

Abstract: The purpose of the present invention is to provide an LED drive circuit that is capable of ameliorating insufficient lighting and improving power utilization efficiency. This LED drive circuit is an LED drive circuit wherein the number of LEDs that are turned on varies in accordance with the voltage of a commercial alternating-current power supply, the LED drive circuit being characterized by having an LED row in which multiple LEDs are connected in series, a current detection resistor for detecting a current that flows in the LED row, a bypass circuit that is connected to an intermediate connection part of the LED row, and a current-limiting circuit that is connected to an end of the LED row, wherein the bypass circuit includes a first current-limiting component, the current-limiting circuit includes a second current-limiting component, the first current-limiting component is controlled on the basis of a voltage across the ends of the current detection resistor or a voltage that is obtained by dividing the voltage across the ends of the current detection resistor, and the second current-limiting component is controlled by the divided voltage that is obtained by dividing the current detection resistor.

Gate drive circuit of the voltage drive type semiconductor element and power converter

Abstract: A power converting apparatus having a gate drive circuit including a push-pull circuit (10) consisting of two transistors (2, 3) at its output stage; a diode (5) connected in series with the push-pull circuit (10); a gate power source (1) connected in parallel with the series circuit of the push-pull circuit (10) and the diode (5); a negative voltage generating circuit (6) connected in parallel with the push-pull circuit (10); a transistor (4) connected between the output terminal of the negative voltage generating circuit (6) and the negative terminal of the gate power source (1), wherein the output voltage of the push-pull circuit (10) is switched from positive polarity to negative polarity and vice versa depending on the signal applied to the base terminals of the transistors (2, 3, 4).

Constant-temperature piezoelectric oscillator and method of manufacturing the same

Abstract: A constant-temperature piezoelectric oscillator includes: a piezoelectric vibrator; an oscillation circuit; a frequency voltage control circuit; a temperature control section; and an arithmetic circuit, wherein the temperature control section includes a temperature-sensitive element, a heating element, and a temperature control circuit, the frequency voltage control circuit includes a voltage-controlled capacitance circuit capable of varying the capacitance value in accordance with the voltage, and a compensation voltage generation circuit, and the arithmetic circuit makes the compensation voltage generation circuit generate a voltage for compensating a frequency deviation due to a temperature difference between zero temperature coefficient temperature Tp of the piezoelectric vibrator and setting temperature Tov of the temperature control section based on a frequency-temperature characteristic compensation amount approximate formula adapted to compensate the frequency deviation, and then applies the voltage to the voltage-controlled capacitance circuit to compensate the frequency.

A CMOS Highly Linear Digitally Programmable Active-RC Design Approach

Abstract: A new approach providing the active-RC integrator with programmable time constant is proposed. An inherently linear current division network (CDN) preserving the high linearity property of the active RC technique while providing wide tuning characteristics is adopted. The proposed integrator provides wider tuning range, and higher tuning resolution accompanied with better linearity and/or reduced area than what could be obtained from capacitor and resistor banks. The proposed integrator uses two opamps per integrator just like its MOSFET-C counterpart but it inherently exhibits better linearity and wider tuning range particularly for low voltage supply. A reconfigurable filter exhibiting complex bandpass and normal lowpass responses is realized. Experimental results obtained from a 4th-order filter fabricated in a standard 0.18 μm CMOS process are given. The complex and lowpass filters achieve in-band spurious-free dynamic ranges (SFDRs) of about 70 dB and 71 dB for bandwidths of 1 MHz and 5.5 MHz, respectively.

Active-RC filters using two-stage OTAs with and without feed-forward compensation

Abstract: In this study, the design of active-RC filters using opamps with and without feed-forward-compensation is considered. Accurate analysis of the passive compensation scheme suggested in literature for lossless and lossy integrators using feed-forward-compensated opamps is carried out. The compensation for the lossy and lossless integrators using negative impedance converter for active filters using two cascaded gm s in place of opamps is explored. Novel building blocks for realising the negative capacitance needed for exact compensation are proposed. To study the efficacy of the proposed compensation technique, a two-integrator loop biquad is considered. The PSPICE simulation results of Tow-Thomas biquad are presented to highlight the performance improvement obtained using the proposed compensation techniques.

Passive Equalizer Design for Through Silicon Vias With Perfect Compensation

Abstract: This paper proposes a novel passive equalizer which is composed of a parallel resistance-capacitance (RC) circuit and capable of perfect compensation for lossy effects of through silicon via (TSV). To design the equalizer, the conventional transmission line theory is utilized to derive an analytic circuit model of the TSV which is verified by numerical methods. Based on the analytic circuit model, the significance analysis is performed to acquire a much simplified capacitance-conductance circuit model which is employed to construct the design formula for the RC equalizer with perfect compensation. A ten-stacked TSV in series with the designed equalizer is taken as an example to demonstrate the resultant improvement in the eye diagram, namely, nearly zero timing jitter and three times enlarged eye opening.

Capacitive to voltage sensing circuit

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Multi-phase synthetic ripple power converter

Abstract: A novel method to operate synthetic ripple multi-phase switching power converters at constant frequency is presented. The method includes the means for sensing the current in each phase without adding extra dissipation and for balancing the currents by affecting the synthetic ripple signal to modulate the duty cycle without disturbing the overall output voltage regulation. Furthermore a method for obtaining optimum load transient response is presented. The method includes the means for simply determining the derivative of the synthetic ripple signal and for forcing maximum duty cycle until the derivative of the synthetic ripple signal reaches a certain threshold. A variant of this method improves further the load transient response by coupling an RC network to the ramp signal generated to modulate the duty cycle so as to maintain the maximum duty cycle a bit longer after the derivative of the synthetic ripple signal has reached the zero value.

Converter circuit and electronic system comprising such a circuit

Abstract: The invention relates to a converter circuit (2) to be connected to an electric power source (3) capable of large fluctuations, including: a chopping circuit (11) including an input terminal (9) connectable to said electric power source (3); a first output circuit (14) connectable via a first switch (17) to an output terminal (19) of the chopping circuit (11); a second output circuit (15) connectable via a second switch (25) to the output terminal (19) of the chopping circuit (11); a control circuit (51) for controlling the duty cycle of the chopping circuit (11) according to the change in voltage of said electric power source (3), as well as the switching of the first (17) and second switches (25) according to a range of output voltage set values for the first output circuit (14).

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

Abstract: In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.

Constant current circuit and reference voltage circuit

Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.

Step-up/down dc-dc converter and switching control circuit

Abstract: A step-up/down DC-DC converter and switching control circuit are described. According to one implementation, a switching control circuit generates on/off signals of a first switching device supplying a current to a voltage conversion inductor of a step-up/down DC-DC converter and a second switching device receiving a current from the inductor. The switching control circuit includes an error amplifier circuit, an inverter amplifier circuit, a waveform generator circuit, a first voltage comparator circuit, a second voltage comparator circuit, and a voltage generator circuit. An inverting reference voltage supplied to the inverting amplifier circuit is set to an electric potential so as not to fall below a highest electric potential of triangle waves supplied to the first and second voltage comparator circuits.

Model order reduction for multi-terminals systems : with applications to circuit simulation

Abstract: Ever since its beginnings in the 1950’s, the integrated circuit (IC) has profoundly changed our lives. The way we work, travel, communicate, or address medical problems today has been facilitated by advances in microelectronics, which permit more functionality to be built on the same silicon area, at decreasing cost. As the feature size of devices on a chip shrink and circuits operate at increasing frequencies, the electromagnetic coupling effects between different IC components can no longer be ignored. To understand their impact on chip performance, these so called parasitic effects must be simulated. Parasitic networks are often so large, that state of the art simulation tools are insufficient to handle them: the simulations are either too lengthy, or cannot be carried out at all. The mathematical reason behind this is that the underlying systems are too large to be solved with the numerical algorithms implemented in simulation software. Model order reduction (MOR) provides one avenue for enabling faster simulations at little accuracy loss. However, when the systems have many input/output nodes, i.e., they have many terminals, performing the reduction itself becomes even more challenging. In this thesis model reduction methods are developed for multi-terminal systems arising in industrial problems. To solve these effeciently, the methods rely jointly on concepts from numerical linear algebra, electrical engineering, and computer science. This thesis begins with an overview of MOR in Chapter 1 and places the reduction of multi-terminal systems in the context of existing approaches. Aside from being efficient and accurate, multi-terminal MOR methods should also ensure that the reduced model is easily inserted in the simulation environment in place of the original, and that it is indeed cheaper to simulate. Although all reduction methods are expected to satisfy these properties, this thesis shows that such expectations are rarely met when traditional approaches are applied to very large electrical networks with many terminals which arise in industrial problems. Hence, an improved framework for multi-terminal model reduction and synthesis is proposed. The methods developed in this thesis address three global problems: (1) the efficient and accurate reduction of multi-terminal circuits, (2) the appropriate synthesis of the reduced model into a netlist equivalent with the same terminal nodes, and (3) the re-simulation of the reduced circuit (instead of the original) with emphasis on accuracy and simulation time. In Chapter 2, a basic framework is developed for the reduction of multi-terminal networks and the synthesis of reduced multi-terminal models. Chapter 2 shows that, if the circuit equations are prepared appropriately, a multi-terminal RLC network can be reduced so that the synthesis step is also greatly simplified. In particular, from the reduced mathematical construction, an equivalent circuit containing only RLC elements can be obtained, without introducing unintended circuit elements such as controlled sources. In addition, the reduced circuit has the same terminal nodes as the original and is coupled easily to other circuit blocks in the simulation setup. The framework establishes the mathematical principle which allows voltage sources, non-linear devices or other parts of a larger network to be de-coupled from to specific linear part to be reduced. It also ensures that these elements can be re-coupled in the simulation phase to the reduced circuit via its terminals. In Chapters 3 and 4, new methods for reducing large, multi-terminal R, and RC networks are derived, with emphasis on accuracy, efficiency and sparsity. It is shown that, if the projection which reduces an R/RC network performs a Schur-complement operation on the original conductance matrix, the resulting reduced network will have only positive resistors, which may be important for certain circuit simulators. This projection is also shown to exactly preserve the path resistance between terminals, and for RC circuits, the slope of the response in addition (in system theoretic terms, two multi-port admittance moments at DC are matched). The efficiency and sparsity considerations are dealt with especially in Chapter 4. These become critical for circuits with terminal numbers exceeding thousands, and node numbers exceeding hundreds of thousands. Reducing them by traditional means is either inefficient, or results in dense reduced models which are more expensive to simulate than the originals. Chapter 4 however develops a new method which is able to reduce efficiently such challenging RC netlists, while ensuring that the reduced models are sparse and fast to simulate. The key principles of the approach are graph partitioning, fill-reducing node re-orderings, and a reducing projection which is constructed accordingly. This preserves sparsity and also maintains accuracy by moment matching irrespective of how the circuit is partitioned. Based on the result of Chapter 2, the reduced models thus obtained are synthesized without controlled sources, have the same terminal nodes as the original ones, and are therefore inserted easily in the desired simulation flow. With the decrease of transistor feature sizes and increase of operating frequencies, it becomes important to also investigate the effects of parasitic inductances (e.g., skin or proximity effects) on chip performance. This requires time-consuming simulations of very large multi-terminal RLC(K) networks, and thus motivates the need for appropriate reduction methods. Chapter 5 identifies the main challenges of multi-terminal RLC reduction, and presents a skeleton for approaching them based on partitioning principles similar to those of Chapter 4. Important problems pertaining to RLC reduction are also identified in Chapter 5, which are otherwise rarely explicitly addressed in the literature. These include matching the response at DC when the underlying conductance matrix is singular, or the presence of singularities in the reduced conductance matrix which in turn negatively affect the simulation of the reduced model. For the latter problem especially, a solution is proposed in Chapter 5 . Two constraints which are known to limit the applicability of traditional reduction methods to multi-terminal systems are as follows: (a) the underlying matrix pencils are often singular and (b) the reducing projections may destroy the structure of the input/output matrices and with that, the physical interpretation of terminal nodes. The advanced methods of Chapters 3, 4 and 5 automatically by-pass these limitations due to the special way in which the reducing projection is formed. Chapter 6 brings an additional contribution by showing how, despite the known limitations, more general reduction methods (e.g., the Loewner approach) are also able to handle multi-terminal systems. The new reduction-synthesis framework of Chapter 6 eliminates the pencil singularity using a simple pre-processing of the original circuit, and recovers the connectivity at all terminal nodes using a post-processing of the reduced model. Among the main results of this thesis is the improvement in reduced model sparsity and reduction efficiency, achieved with the help of graph partitioning. State-of-theart partitioning algorithms such as nested dissection or Mondriaan already served this purpose, nevertheless Chapter 7 shows that the results could be further strengthened with the help of partitioning criteria designed especially for multi-terminal MOR. A high level description of the desired objectives is also derived there.

Monolithic RC-snubber for power electronic applications

Abstract: In this work, we present a monolithic RC-snubber for power electronic applications that outperforms state of the art RC-snubbers in terms of characteristic electrical parameters. The principle device structure as well as the process technology is presented. The outstanding properties of the device are a high capacitance per area (1.5 nF/mm2), a low temperature coefficient of the capacitance value (85 ppm/°C) and a low leakage current (<1 nA) for voltages up to 250 V. Characteristic electrical parameters of the single device and in a typical application are shown. In comparison to a SMD snubber, the monolithic RC-snubber shows a significant reduction of overvoltage during switching and enhanced electromagnetic noise suppression.

Constant current led lamp

Abstract: A constant current LED lamp is provided with a linear driver circuit for driving multiple light emitting diodes (LEDs), or LED packages including multiple LED chips, connected in series The driver circuit includes a rectifier circuit, a filter circuit, a stable voltage circuit, and a constant current circuit The driver circuit allows the aggregate forward voltage drop of all the LEDs connected in series to approach the rectified input voltage to efficiently utilize the AC power from the mains

A New Low-Voltage Current Mirror Circuit with Enhanced Bandwidth

Abstract: In this paper low-voltage current mirror circuit is proposed. The proposed circuit is developed by using four p-type and five n-type MOSFET's. The proposed circuit is operated at the supply voltage of +1.3 volt. The bandwidth of this circuit has also been enhanced using bandwidth enhancement technique. The proposed circuit has been simulated using Cadence Design Environment in the UMC 0.18 µm CMOS technology. The simulation results have been presented to validate the effectiveness of the proposed circuit.