Showing papers on "RC circuit published in 2012"

A coherent RC circuit

Abstract: We review the first experiment on dynamic transport in a phase-coherent quantum conductor. In our discussion, we highlight the use of time-dependent transport as a means of gaining insight into charge relaxation on a mesoscopic scale. For this purpose, we studied the ac conductance of a model quantum conductor, i.e. the quantum RC circuit. Prior to our experimental work, Buttiker et al (1993 Phys. Lett. A 180 364–9) first worked on dynamic mesoscopic transport in the 1990s. They predicted that the mesoscopic RC circuit can be described by a quantum capacitance related to the density of states in the capacitor and a constant charge-relaxation resistance equal to half of the resistance quantum h/2e2, when a single mode is transmitted between the capacitance and a reservoir. By applying a microwave excitation to a gate located on top of a coherent submicronic quantum dot that is coupled to a reservoir, we validate this theoretical prediction on the ac conductance of the quantum RC circuit. Our study demonstrates that the ac conductance is directly related to the dwell time of electrons in the capacitor. Thereby, we observed a counterintuitive behavior of a quantum origin: as the transmission of the single conducting mode decreases, the resistance of the quantum RC circuit remains constant while the capacitance oscillates.

Conducted Common-Mode EMI Reduction by Impedance Balancing

Abstract: A new method to reduce common-mode (CM) electromagnetic interference (EMI) emission at the dc input of variable-speed motor drives is presented. Unlike conventional passive or active filtering techniques that rely on impedance mismatch or active noise cancellation, the proposed method uses a passive circuit with matched impedance to cancel the inverter CM current. In the proposed approach, a star-connected three-phase RC circuit is placed at the output of the inverter to extract the CM voltage. An inductor is connected between the star point of the RC circuit and the middle of the dc bus capacitor to inject a CM current into the dc input. A Wheatstone bridge is then identified in the CM equivalent circuit of the system with these additional components. By properly selecting the inductor, the Wheatstone bridge can be balanced, resulting in near-ideal cancellation of the input CM current. Development of the method is presented and an experimental setup is used to demonstrate its effects. A comparison with conventional EMI filtering methods in terms of overall filter volume is also presented.

Compact Thermal Resistor-Capacitor-Network Approach to Predicting Transient Junction Temperatures of a Power Amplifier Module

Abstract: Junction temperature is an important issue for a semiconductor package, influencing the package's thermal, mechanical, and reliability performance. An accurate prediction of junction temperature provides informative guidance in design, development and operation of the package. A compact thermal resistor-capacitor (RC) network approach is presented in this paper to accurately predict transient junction temperatures. The thermal RC network in this approach is a nongrounded Foster network. This approach consists of extraction of the thermal Foster network and prediction of the transient junction temperature response to a given power input using the extracted network. The network extraction part is based on Kirchhoff's current law and Laplace transformation technique, and uses the Foster network to facilitate changes of the RC network structure. The temperature prediction part is a direct substitution-and-calculation process, and therefore is fast to carry out. Since Laplace transforms are directly or indirectly available for most power inputs, their transient temperatures may be predicted by the proposed approach. Superposition is employed in cases where the Laplace transform of a given power input is not directly found in Laplace tables, or where the junction temperature is affected by multiple heat sources. The proposed approach is demonstrated with a power amplifier (PA) module; predicted junction temperatures are accurate in both single and multiple heat source cases.

An Ultra-Compact, Linearly-Controlled Variable Phase Shifter Designed With a Novel RC Poly-Phase Filter

Abstract: This paper proposes a new vector-sum type variable-phase shifter (VPS) topology for predistorting the phase of a modulated signal for an analog-predistortion power amplifier system It has a continuous linear-in-degree control curve over a 90° phase-control range and has the smallest size among all those proposed CMOS works The phase shifter utilizes an improved RC poly-phase filter to generate in-phase and quadrature-phase vectors It uses fewer RC components but has a wider phase-splitting bandwidth than traditional RC filters, reducing the loss and size of the overall VPS Specially-designed control circuits give the shifter a linear phase-control capability, minimizing the gain variation over the phase-control range The phase shifter, optimized for WCDMA applications, has been fabricated in a standard 018-μm CMOS process The area of the phase shifter core is 0063 mm2 The measured operation frequency is from 1 to 21 GHz, which is an overlap of its 3-dB cutoff frequency and bandwidth of a 90° phase-control range Within the bandwidth, this phase shifter displays a linear control curve with phase errors of less than ±1° over a 70° tuning range, making it suitable for accurate AM-PM error compensation

A 1-to-2.5GHz phased-array IC based on g m -RC all-pass time-delay cells

Abstract: Electronically variable delays for beamforming are generally realized by phase shifters. Although a constant phase shift can approximate a time delay in a limited frequency band, this does not hold for larger arrays that scan over wide angles and have a large instantaneous bandwidth. In this case true time delays are wanted to avoid effects such as beam-squinting. In this paper we aim at compactly integrating a delay based phased-array receiver in standard CMOS IC technology. This is for instance relevant for synthetic aperture radars, which require large instantaneous bandwidths often in excess of 1GHz, either as RF or as IF bandwidth in a superheterodyne system. We target low-GHz radar frequencies, assuming sub-arrays of four elements and up to 550ps delay.

Driver circuit for reduced form factor solid state light source lamp

Abstract: A solid state light source driver circuit, system and method are provided. The driver circuit includes a rectifier circuit, an energy storage element coupled thereto, a current bleeder circuit coupled thereto, and a switch. The rectifier circuit receives AC input and provides unregulated DC voltage. The switch closes to couple some of the unregulated DC voltage to the energy storage element, and opens to transfer energy to drive the light source. A power factor controller circuit provides an output signal to control the switch. The current bleeder circuit provides supply voltage to the power factor controller circuit within a range and maintains a current flow associated with the AC input that exceeds a predetermined threshold. A constant off-time controller circuit provides a switching frequency control signal to the power factor controller circuit. An EMI filter reduces generated EMI noise.

VLSI Analog Filters : Active RC, OTA-C, and SC

Abstract: I. Introduction.- II. Active RC filters.- III. OTA-C filters.- IV. SC filters.- V. Practical designs of VLSI analog filters.- Appendix A.- Appendix B.

Real time battery power capability estimation

Abstract: Accurate battery power capability estimation is a key to battery life and performance in electric and hybrid vehicles. If power capability is predicted to be higher than actual, battery life is reduced and there is potential for vehicle shutdown. If power capability is predicted lower than actual, the customer may experience slower acceleration, lower top speed, and reduced usable electric drive range. In this paper an approach is proposed to estimate lithium-ion battery charge and discharge power capabilities online. First a simplified Randles circuit model is used to represent a battery cell. Then an Extended Kalman Filter (EKF) is constructed to estimate the model parameters and voltage across the RC network. Algorithms to calculate the charge and discharge power capabilities are presented. Both desktop simulation and pack level vehicle data are shown to support the correctness and accuracy of the proposed algorithms.

Power supply circuit system

Abstract: A power supply circuit system includes a ring oscillator provided with a variable resistance circuit, a charge pump circuit outputting a boosted voltage in response to an oscillation output signal from the ring oscillator, a voltage regulator circuit adjusting the boosted voltage from the charge pump circuit, a first current comparator circuit comparing a first current flowing through the voltage regulator circuit with a first reference current, a second current comparator circuit comparing the first current with a second reference current, and a control circuit outputting control signals to control a resistance value of the variable resistance circuit in accordance with a first comparison signal from the first current comparator circuit and a second comparison signal from the second current comparator circuit

Resonant dc converter

Abstract: A resonant DC converter, combines a voltage type auto charge pump circuit with a full-bridge or half-bridge resonant DC conversion circuit at a primary side of a transformer, combines a double-voltage rectifier circuit at a secondary side of the transformer, and grants the circuit of the invention with characteristics of variable circuit architecture by means of the design of circuit parameters and the action of the LC resonant circuit. Integration of switching elements of the converter circuit and the use of characteristics of automatically changing the circuit architecture contribute to reduce the switching losses and increase the circuit conversion efficiency. Low output voltage ripple enables the circuit of the invention to avoid using large-capacitance electrolytic capacitors and be able to extend the service life of the transformer. The operation of the circuit of the invention at boost or buck mode can be controlled by adjusting the circuit parameters.

Minimum DC-link voltage design of three-phase four-wire active power filters

Abstract: This paper presents a minimum dc-link voltage design for three-phase four-wire center-split active power filters (APFs). According to the current quality data and the APF single-phase equivalent circuit models, the minimum dc-link voltage expression for the APF is deduced and proposed, in which the deduced expression is applicable to single-phase and three-phase four-wire APF systems. Representative simulation results of the three-phase four-wire APF are presented to verify the minimum dc-link voltage expression.

Electro-thermal modeling of power LED using SPICE circuit solver

Abstract: This paper presents a method of multi-domain modeling for power Light Emitting Diodes (LEDs) with the goal of providing the ability for simultaneous simulations of electrical, thermal and optical behavior. This approach enables engineers to have a better insight into LED critical performance parameters in various operating conditions, by considering the main electrical-thermal and optical interactions. Our proposed multi-domain model integrates an electrical model based on typical diode equations, a dynamic thermal model composed of a Cauer type RC network driven by currnet source, and an optical model derived from the forward current and junction temperature variations of the total luminous flux. The presented approach offers three significant advantages over the traditional single-domain modeling: the effects of packaging and board level thermal management can be evaluated in correlation with electrical parameters, the self heating effect of the junction can be analyzed in the time domain, and the variation of luminous flux output can be observed. The model is defined based on SPICE circuit elements and can be used with any conventional SPICE circuit solver, without the need for solver algorithm modification. The inputs necessary for defining the model are based on standard LED measurements and are often specified in the manufacturer's datasheets. All the necessary algorithms required to obtain the multi-domain model SPICE code were implemented in Matlab.

Anticipating, complete and lag synchronizations in RC phase-shift network based coupled Chua's circuits without delay

Abstract: We construct a new RC phase shift network based Chua’s circuit, which exhibits a period-doubling bifurcation route to chaos. Using coupled versions of such a phase-shift network based Chua’s oscillators, we describe a new method for achieving complete synchronization (CS), approximate lag synchronization (LS), and approximate anticipating synchronization (AS) without delay or parameter mismatch. Employing the Pecora and Carroll approach, chaos synchronization is achieved in coupled chaotic oscillators, where the drive system variables control the response system. As a result, AS or LS or CS is demonstrated without using a variable delay line both experimentally and numerically.

All-MOS implementation of RC networks for time-controlled Gaussian spatial filtering

Abstract: This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2-node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analyzing them from a stochastic point of view. Following the design methodology proposed, the error committed by an MOS-based grid when compared with its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS-OPTO process. This prototype incorporates a focal-plane MOS-based RC network that performs fully programmable Gaussian filtering. Copyright © 2011 John Wiley & Sons, Ltd.

Enhanced efficiency low-dropout linear regulator and corresponding method

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases

Digital phase adjustment for multi-phase power converters

Abstract: A multiphase power converter includes one or both of a phase control circuit and a valley switching locking circuit. The phase control circuit measures a phase difference between a first phase circuit and a second phase circuit and varies an on-time of a drive switch of the second phase circuit to produce and maintain a predetermined phase difference between the first phase circuit and the second phase circuit. When the multiphase power converter is operating in a discontinuous mode of operation, the valley switching locking circuit counts the number of zero crossings of an input current of the first phase circuit and blocks a second zero crossing detection signal from a waveform generator (i.e., PWM driver) associated with the second phase circuit until an input current of the second phase circuit has as many zero crossings as that of the first phase circuit input current.

Characterization of aging process in power converters using spread spectrum time domain reflectometry

Abstract: This paper aims to find a new technique to predict the state of health of power converters by characterizing the most vulnerable components in the converter without affecting the normal circuit operation. Spread spectrum time domain reflectometry (SSTDR) can detect most of the aged components inside the converter while the converter is operational. Semiconductor switches and electrolytic capacitors are the two most sensitive components in power converter circuits, and this paper demonstrated how SSTDR can be used to determine the degradation of these components. Multiple sets of test data have been generated while the SSTDR process is applied to the power MOSFETs, IGBTs connected in a chopper circuit and to the aluminum electrolytic capacitors connected in an RC circuit. Analysis is done on these obtained test data to show how the SSTDR generated data are consistent with the aging of power MOSFETs, IGBTs and electrolytic capacitors.

A New Approach to Implementing High-Frequency Correlated Noise for Bipolar Transistor Compact Modeling

Abstract: A new approach to implementing correlated high-frequency noise in bipolar junction transistor (BJT) large-signal compact models is developed by placing an RC -delayed noise current between the base and collector nodes. The approach reproduces the two stages of noise transport in a BJT, i.e., noise generation in the base and emitter and transportation through the collector-base junction space-charge region (CB SCR). The frequency dependence of the intrinsic noise sources due to the CB SCR is fully described with an accuracy value up to the second order of ω. As an example, the negative frequency dependence of Sic is correctly described for the first time. The approach is applicable to any large-signal compact model, and it is demonstrated using measurement data in both InGaP/GaAs heterojunction bipolar transistors (HBTs) and SiGe HBTs.

Impedance-matching switching circuit, antenna device, high-frequency power amplification device, and communication-terminal device

Abstract: An antenna device (101) comprising a radiating element (11) and an impedance-matching switching circuit (14) connected to a power-supply circuit (30). Said impedance-matching switching circuit (14) matches the impedance of a second high-frequency circuit element, namely the radiating element (11), to that of a first high-frequency circuit element, namely the power-supply circuit (30). The impedance-matching switching circuit (14) comprises a transformer matching circuit (15) and a series active circuit (16); said transformer matching circuit (15) matches the real part of the impedance and the series active circuit (16) matches the imaginary part. This allows impedance matching over a wide frequency band at a point where high-frequency circuits or elements having different impedances are connected to each other.

A 4.75–34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS

Abstract: A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75–34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.

Peak current control device and method for switching power supply

Abstract: A switching mode power supply with improved peak current control is disclosed A varying reference signal is adopted to limit the peak current in the energy storage component The varying reference signal is an exponential function of a time period when a power switch is ON, wherein the power switch is coupled to the energy storage component The varying reference signal may be generated by a circuit comprising a RC circuit and one or several voltage sources

Ultralow-Power Processing Array for Image Enhancement and Edge Detection

Abstract: This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can also be attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for VGA-resolution array processing images at 30 fps is 570 μW.

Circuit simulation model of capacitor, constructing method of simulation model, method of circuit simulation, circuit simulator

Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.

Method and apparatus for implementing slew rate control using bypass capacitor

Abstract: An example circuit includes a capacitance circuit, a regulator circuit, and a slew rate control circuit. The capacitance circuit is coupled between a first node and a second node. The regulator circuit is coupled to the capacitance circuit to regulate a supply voltage across the capacitance circuit with a charge current during a normal operation mode of the circuit. The slew rate control circuit is coupled to the capacitance circuit and the regulator circuit. The slew rate control circuit is coupled to lower a slew rate of a change in voltage over change in time between the first and second nodes during a power up mode of the circuit. The slew rate control circuit includes a transistor coupled between the first and second nodes to shunt excess current from the charge current.

MR16 LED lamp drive circuit, drive method and MR16 LED lamp illumination system applying MR16 LED lamp drive circuit

Abstract: The invention relates to an MR16 LED lamp drive circuit and a drive method. The MR16 LED lamp drive circuit provided by the invention comprises an RC (Resistance-Capacitance) network, a primary voltage conversion circuit and a secondary voltage conversion circuit, wherein the first end of the RC network is connected to the first output end of a rectifying circuit, and the second end of the RC network is connected to the ground, so that DC voltage is converted into smooth input voltage; the primary voltage conversion circuit is connected with the RC network so as to receive the input voltage and convert the input voltage into first output voltage; and the secondary voltage conversion circuit is connected with the primary voltage conversion circuit so as to receive the first output voltage and convert the first output voltage into second output voltage for driving an MR16 LED lamp.

Frequency domain characterization of a solar cell

Abstract: The generation of a small signal dynamic model of a solar cell was investigated. As a starting structure the usual one diode large signal dynamic model was used with known parameter values. A simple parallel linear RC circuit was used to represent the model while the element values were put to be functions of the illumination here represented by the photo-current. The element value versus photocurrent dependences were captured by artificial neural networks one per element. Verification of the model was performed by comparisons of the responses of the original nonlinear dynamic model and the linear RC model to a chirp signal of small amplitude.

CMOS Current-Mode Implementation of Fractional-Power Functions

Abstract: A CMOS current-mode circuit, with only eight transistors and two current sources, is proposed to implement a fractional power function. The compact circuit comprises of an approximating logarithm circuit and an approximating exponential circuit. By sizing one transistor and tuning one current source, we improve the truncation errors in the Taylor series approximation, and reduce the MOS square-law errors that are caused by second-order effects. As example, a circuit, designed for gamma correction, with different gamma values controlled by three switches, is fabricated using 0.35 μm CMOS technology. The demonstration circuit can achieve a bandwidth of 155 MHz for an input range from 40 μA to 130 μA with 3% error, and maximum power dissipation of approximately 970 μW.

Automated knowledge–based filter synthesis using modified Legendre approximation and optimisation of summed sensitivity

Abstract: The paper presents the automated design of active RC and programmable filters. The approximating function is derived using Legendre orthogonal polynomial with the appropriate weights and usage of two Legendre multiplication factors at the origin and the pass–band edge frequency. Detailed analysis is done for the frequency response and sensitivity analysis of active RC filters. Optimisation is performed using symbolic manipulation of expressions inputted into computer algebra system and numeric solvers. The code is in the form of template notebook, and the user should specify the minimal number of numeric values, such as the number of second–order filter sections, the pass–band edge frequency, the reflection coefficient, and the preferred values of component values.