Showing papers on "RC circuit published in 2018"

Characterisation and Modeling of Gallium Nitride Power Semiconductor Devices Dynamic On-State Resistance

Abstract: Gallium nitride high-electron-mobility transistors (GaN-HEMTs) suffer from trapping effects that increases device on-state resistance ( $R_\mathrm{DS(on)}$ ) above its theoretical value. This increase is a function of the applied dc bias when the device is in its off state, and the time which the device is biased for. Thus, dynamic $R_\mathrm{DS(on)}$ of different commercial GaN-HEMTs are characterised at different bias voltages in the paper by a proposed new measurement circuit. The time-constants associated with trapping and detrapping effects in the device are extracted using the proposed circuit and it is shown that variations in $R_\mathrm{DS(on)}$ can be predicted using a series of RC circuit networks. A new methodology for integrating these $R_\mathrm{DS(on)}$ predictions into existing gallium nitride-high-electron-mobility transistors models in standard SPICE simulators to improve model accuracy is then presented. Finally, device dynamic $R_\mathrm{DS(on)}$ values of the model is compared and validated with the measurement when it switches in a power converter with different duty cycles and switching voltages.

A Physical RC Network Model for Electrothermal Analysis of a Multichip SiC Power Module

Abstract: This paper is concerned with the thermal models which can physically reflect the heat-flow paths in a lightweight three-phase half-bridge two-level SiC power module with six MOSFETs and can be used for coupled electrothermal simulation. The finite-element (FE) model was first evaluated and calibrated to provide the raw data for establishing the physical resistor–capacitor (RC) network model. It was experimentally verified that the cooling condition of the module mounted on a water cooler can be satisfactorily described by assuming the water cooler as a heat exchange boundary in the FE model. The compact RC network consisting of 115 R and C parameters to predict the transient junction temperatures of the six MOSFETS was constructed, where cross-heating effects between the MOSFETs are represented with lateral thermal resistors. A three-step curve fitting method was especially developed to overcome the challenge for extracting the R and C values of the RC network from the selected FE simulation results. The established compact RC network model can physically be correlated with the structure and heat-flow paths in the power module, and was evaluated using the FE simulation results from the power module under realistic switching conditions. It was also integrated into the LTspice model to perform the coupled electrothermal simulation to predict the power losses and junction temperatures of the six MOSFETs under switching frequencies from 5 to 100 kHz which demonstrate the good electrothermal performance of the designed power module.

Ultra-high-speed graphene optical modulator design based on tight field confinement in a slot waveguide

Abstract: We present a design of an ultra-fast in-line graphene optical modulator on a silicon waveguide with a bandwidth exceeding 100 GHz, very small power consumption below 15 fJ/bit, and insertion loss of 1.5 dB. This is achieved by utilizing the transverse-electric-mode silicon slot to tailor the overlap of graphene electrodes, thus significantly reducing the capacitance of the device while maintaining a low insertion loss and using conservative estimates of the graphene resistance. Our design is substantiated by comprehensive finite-element-method simulations and RC circuit characterization, as well as fabrication feasibility discussion.

Computational intelligence methodology for the analysis of RC circuit modelled with nonlinear differential order system

Abstract: In this study, we solve nonlinear initial value problems arising in circuit analysis by applying bio-inspired computational intelligence technique using feed-forward artificial neural networks (ANNs) optimized with genetic algorithms (GAs), sequential quadratic programming (SQP), and their combined scheme. The system of resister–capacitor (RC) circuit having nonlinear capacitance is mathematically modelled with unsupervised ANNs by defining an energy function in mean-square error (MSE) sense. The objectives are to minimize the MSE for which the parameters of the networks are estimated initially with GA-based global search and in steady state with SQP algorithm for efficient local search. We consider a set of scenarios to evaluate the performance of the proposed scheme for different resistance and capacitance values along with current variations in the nonlinear RC circuit system. The results are compared with well-established fully explicit Runge–Kutta numerical solver in order to verify the accuracy of the applied bio-inspired heuristics. To prove the worth of the scheme, a comprehensive statistical analysis is provided for the performance metrics based on root MSE, mean absolute error, Theil’s inequality coefficient, Nash–Sutcliffe efficiency, variance account for, and the coefficient of determination (R 2).

Design of Low-Power Low-Area Tunable Active RC Filters

Abstract: A method to design low-power low-area active RC filters is presented. The output voltages of the operational amplifiers are scaled and buffered, allowing the use of single stage topologies for less power consumption and eliminating the compensation capacitor. Tuning of the filter characteristic is also done by switching the currents through the output buffers, which removes the need for capacitor banks. The advantages of the proposed method are incorporated to present a general low-power biquad with small die area. The biquad section is then used to design a low-power baseband filter for Bluetooth receivers with 600-KHz cutoff frequency. The fourth-order filter, fabricated in a 0.18- $ {\mu }\text{m}$ CMOS process, consumes 0.5 mW with a die area of 0.13 mm $^{2}$ .

Carbon Black based capacitive Fractional Order Element towards a new electronic device

Abstract: In this paper, Fractional Order Elements (FOEs), fabricated by using a carbon black nano structured dielectrics, are presented. FOEs have been realized by varying different fabrication parameters such as the percentage of carbon black, the curing temperature, and the solvent type. Results on the experimental frequency characterization of one FOE device are given. The FOE has been, then, used for demonstrating the possibility of realizing a fractional order RC filter. The frequency analysis of the RC filter shows the coherence of the fractional order between the FOE and corresponding RC circuit.

Analysis of equivalent circuit models in lithium-ion batteries

Abstract: This study investigates lithium-ion (Li-ion) battery discharge at a constant current by comparing equivalent circuit simulation data with experimental data. The simulations employ Thevenin equivalent circuit models consisting of a resistance, capacitance, and power source. Voltage and resistance are measured during battery discharge at a constant 2 A direct current (DC). The experimental output results of the resistor-capacitor (RC) circuit are calculated and compared to the simulation results over the time of discharge. Both single and triple RC circuits are utilized in the experiment, with the triple RC circuit model demonstrating less error than the single RC circuit when compared to the simulated data. This study suggests that the output voltage of a Li-ion battery generally obeys a simulated Thevenin equivalent circuit model composed of the multiple RC elements under constant current discharge.

Implementation of real-time digital CR–RCm shaping filter on FPGA for gamma-ray spectroscopy

Abstract: A novel implementation of a digital CR – RC m shaping filter for gamma-ray spectroscopy is presented in this paper, derived from the digitalization and quantization of the input and output voltage of CR and RC circuits. Compared with the conventional digital CR – RC m shaper, it has a relatively simple structure consuming fewer multipliers and is easy to realize on DSP chips. More importantly, this digital shaper also overcomes the shortcoming of the conventional digital CR – RC m shaper, which lacks the function of pole-zero cancellation (PZC). Experimental data on noise suppression, immunity to ballistic deficit, and energy resolution improvement show that the digital spectroscopy system based on the described shaper achieves the same excellent performance as the analog spectroscopy system from CANBERRA, which therefore provides a new way to realize the shaping of digital signals from radiation detectors, and this carries great significance for engineering applications.

A Physics-based Thermal Model of Nanosheet MOSFETs for Device-Circuit Co-design

Abstract: A physics-based thermal model is developed to describe the self-heating effects (SHE) on nanosheet MOSFETs. Three stages of transient temperature response due to the anisotropic heat dissipation and asymmetrical temperature distribution are well understood by the thermal RC network model, providing the physical insight into frequency-dependent SHE in AC operation. The proposed model is further implemented into SPICE simulator for high-efficient thermal assessment in circuit level by the flexible BEOL. Layout design in inverter cell correlated with thermal behavior is investigated for static and transient operation downwards 3nm CMOS node. The SHE and thermal-aware reliability in inverter-based ring oscillator are predicted. The thermal model can be used as a device-circuit co-design tool to assess the thermal behavior accurately and efficiently.

A 45- $\mu$ W, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch

Abstract: An ultra-low-power, start-up and phase noise performance improved 2-stage differential ring voltage-controlled oscillator (VCO) is proposed. The proposed delay cell architecture reduces power consumption by eliminating the cross-coupling latch of the conventional ring VCO. Instead of the latch, the inverters in the proposed delay cell produce negative conductance by insertion of an additional RC network, which improves the start-up performance of the proposed VCO. The proposed delay cell architecture also improves the phase noise performance of the VCO as it sharpens the drain current of the inverter stage such that it resembles an impulse waveform, which reduces the root-mean-square value of impulse sensitivity function. Implemented in a 65-nm CMOS technology, the measured phase noise of the proposed VCO at 1 MHz offset is −94.84 dBc/Hz at 490 MHz oscillation frequency while dissipating 45 $\mu \text{W}$ from a 0.6-V supply. The figure of merit is 162.1 dBc/Hz.

Accurate SPICE Model of Forward-Biased Silicon PIN Mach–Zehnder Modulator for an Energy-Efficient Multilevel Transmitter

Abstract: A precise device model of a silicon forward-biased PIN phase shifter was developed to realize a codesign of an integrated multilevel optical transmitter combining a compact silicon-based Mach–Zehnder modulator (MZM) and a low-power CMOS driver circuit by utilizing SPICE simulation. Both electric and optical responses of the PIN phase shifter were carefully investigated at various bias conditions and temperatures in order to build a SPICE device model that precisely emulates a highly nonlinear electric-to-optical (EO) response of the PIN phase shifter. The validity of the developed model was assessed for a dc response, small-signal RF electric, and optical responses, and also for large-signal EO responses. The simulation outputs exhibited very good agreement with the responses measured at each operation condition. Using this PIN phase shifter model, we designed a multilevel optical transmitter integrating a 750-μm long silicon PIN-based MZM with a 28-nm CMOS driver circuit via passive RC circuit equalizers. The SPICE simulation demonstrated the feasibility of the integrated transmitter for 56 Gbps PAM4 operation with a very high energy efficiency: 1.2 mW/Gbps.

Advancements in the identification of passive RC networks for compact modeling of thermal effects in electronic devices and systems

Abstract: We deal with the problem of identifying the parameters of an equivalent lumped RC multiport network from time domain tabulated data of a corresponding distributed real eigenvalues problem, as obtained from either measurements or accurate simulation tools. A novel step response matrix identification procedure is proposed, based on the combination of an outer nonlinear least squares iteration for the relocation of time constants, and an inner convex programming cycle for the identification of the corresponding residue matrix terms, able to guarantee a priori the passivity property of the equivalent RC network. The structure of the algorithm and its principal functions connections are shown, and the mathematical features of the proposed formulation of the identification problem are accurately described and commented. Moreover, the possibility of getting direct synthesis of a Foster generalized concretely passive multiport, as a consequence of the optimal identification of a passive real eigenvalues model from data, is discussed. Since the technique is well suited (although not limited) to the reduced analysis of typical electro-thermal problems, a set of significant case studies in this area is considered. In this way the algorithm present implementation is validated, also comparing it to previous well assessed methods, evidencing its large potential and value.

CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator

Abstract: This paper deals with CMOS fractional-order inductance $(FoL)$ simulator design and its utilization in $2.75^{th}-$ order Colpitts oscillator providing high frequency of oscillation. The proposed floatingFoL is composed of two unity-gain current followers $(CF \pm s)$, two inverting voltage buffers, a transconductor, and a fractional-order capacitor $(FoC)$ of order 0.75, while the input intrinsic resistance of $CF \pm$ is used as design parameter instead of passive resistor. The resulting equivalent inductance value of theFoL can be adjusted via order of FoC, which was emulated via 5th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 $kHz-2.45$ MHz theL r shows ± 5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 $\mu m$ leve1-7 LO EPI SCN018 CMOS process parameters with $\pm 1V$ supply voltages.

A Novel Autonomous 5-D Hyperjerk RC Circuit with Hyperbolic Sine Function

Abstract: A novel autonomous 5-D hyperjerk RC circuit with hyperbolic sine function is proposed in this paper. Compared to some existing 5-D systems like the 5-D Sprott B system, the 5-D Lorentz, and the Lorentz-like systems, the new system is the simplest 5-D system with complex dynamics reported to date. Its simplicity mainly relies on its nonlinear part which is synthetized using only two semiconductor diodes. The system displays only one equilibrium point and can exhibit both periodic and chaotic dynamical behavior. The complex dynamics of the system is investigated by means of bifurcation analysis. In particular, the striking phenomenon of multistability is revealed showing up to seven coexisting attractors in phase space depending solely on the system’s initial state. To the best of author’s knowledge, this rich dynamics has not yet been revealed in any 5-D dynamical system in general or particularly in any hyperjerk system. Pspice circuit simulations are performed to verify theoretical/numerical analysis.

CMOS-Based Multifrequency Impedance Analyzer for Biomedical Applications

Abstract: In this paper we present a monolithic microsystem, which can perform Bio-Impedance Analysis (BIA), and electro impedance tomography (EIT) measurements as well as record electrocardiogram (ECG) signals. In contrast to a full analog lock-in approach, a mixed analog/digital solution is adopted. The proposed solution has been designed, implemented and tested using a commercial 0.35-μm CMOS technology. The tuning range of the signal generator and the detector is from 10kHz to 10MHz in 1kHz steps. The circuit ensures a CMRR of 81dB@10kHz, which increases to 84dB@10MHz. The measured equivalent input noise power spectral density is en=2.57nV/√Hz at 10kHz in the worst case, close to the 1/f corner frequency. It decreases until en=1.8nV/VHz at 1MHz and en=1.9nV/√Hz at 10MHz. Measurements of a reference RC network performed with the proposed monolithic solution and compared with a Keysight E4980A Precision LCR Meter shows a maximal relative error of 0.8% over the whole operating frequency range.

Estimation for SOC of Li-ion battery based on two-order RC temperature model

Abstract: With energy and environmental problems getting more and more seriously, electric vehicles (EVs) have attracted great attention at home and abroad. This paper mainly studies the battery model and State of Charge (SOC) estimation of EVs. Based on the traditional two-order RC circuit equivalent model, a new two-order RC model considering temperature factor is proposed, and the Extended Kalman Particle Filter (EKPF) algorithm is used to estimate the SOC of battery. Experimental results show that, the two-order RC temperature model has high accuracy, it can simulate the battery state at different temperatures and has a certain practical value.

A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control

Abstract: This paper presents an application of a fractional-order control in an on-chip follower-type 1.8 V/100 mA voltage regulator to achieve a good stability with any load capacitance. The controller approximates an integrator with the fractional order of 0.5, whose phase lag is not more than 45°. The fractional order is set by the fractional-order impedance of the resistive p-type MOS capacitor (R-PMOScap). With an n-type MOS source follower stage adding the phase lag of at most 90°, the remaining phase margin is always at least 45°. The R-PMOScap is a novel integrated distributed-element RC network, realized as a resistive polysilicon strip on a gate oxide, and is compatible with an analog CMOS process. The voltage regulator has been manufactured in a 350-nm CMOS process and occupies a small chip area of 0.038 mm2. It operates in a harsh automotive environment with a temperature from −50 °C to 200 °C and shows a tight DC regulation, while being stable over the full range of the load current (from 0 to 100 mA) and with any load capacitance (allowing to use none or any external capacitor).

Flexible Substrate Based Few Layer MoS2 Electrode for Passive Electronic Devices and Interactive Frequency Modulation Based on Human Motion

Abstract: This paper reports the demonstration of human integrated electronic devices, such as oscillators and RC filters, by utilizing flexible capacitor fabricated using few layer MoS2 grown on Al foil via hydrothermal method as electrodes and cellulose paper as a dielectric material. There are no reports of MoS2 on flexible substrate being utilized as capacitor electrode and further applied human interactive devices. Advantage of using MoS2 on Al foil is the enhanced capacitance upon strain due to the piezoelectric property of few layered MoS2 over monolayer MoS2. As the applied strain increases, increase in the capacitance was observed, which is systematically explained by piezoelectric property of MoS2, change in physical dimensions, and air gap between MoS2–Al foil and cellulose paper. Upon application of external strain on capacitor, range of frequencies can be generated by oscillator circuit and the mathematical operations such as differentiation and integration are observed for different input signal using RC filter circuits. Further, the fabricated flexible MoS2 capacitor was integrated to human hand and the corresponding frequency modulation with hand movement was recorded. Such a simple technique for fabrication of flexible variable capacitor is a major step ahead in wearable electronics having applications in digital electronics and sensors.

Integrated RF Passive Low-Pass Filters in Silicon Photonics

Abstract: The integration of passive radio frequency (RF) components, such as resistors, capacitors, and inductors, requires a relatively large area on complementary metal—oxide—semiconductor chips, which is not cost-effective in developing optical receiver front-ends. This could be addressed by implementing passive RF components on silicon photonics chips. In this letter, we present an on-chip passive RF low-pass filter coupled to an integrated photodetector. This letter demonstrates that passive RF analog processing can be implemented in a commercial silicon photonics platform. The performance of the implemented RC filters is reported at frequencies up to 15 GHz.

Cost-effective fabrication and high-frequency response of non-ideal RC application based on 3D porous laser-induced graphene

Abstract: This work presents a design, fabrication, modeling and frequency response of 3D porous graphene circuit elements for a non-ideal resistor–capacitor (RC) circuit application based on a CO2 infrared laser direct writing method. The material properties of laser-induced graphene (LIG) were carefully analyzed by Raman, SEM and XRD. The room-temperature experiment of the non-ideal RC circuit from 3D porous LIG was conducted by three different electrical frequencies. The results showed that the parallel non-ideal capacitors had ~ 10% electrical response differences than with a single or a series porous graphene capacitor element. Furthermore, we demonstrated that the experiment result and the numerical simulation result of the porous graphene circuit elements were in good agreement. Moreover, the 3D porous graphene-based non-ideal RC circuit was demonstrated a 300 kHz cutoff frequency by an impedance analyzer. Compared with other methods for graphene of circuit elements system, this LIG method not only has the advantage of a one-step processing of 3D porous graphene circuit elements in air, but also provided a rapid realization of graphene-based circuit elements system on polymer.

A Simple Adaptive Fractional Order Model of Supercapacitor for Pulse Power Applications

Abstract: The porous nature of the electrodes results in complex dynamics of the supercapacitors. Consequently, the value of the capacitance varies with the voltage level, frequency and magnitude of the charging/discharging current. Conventional RC models or ladder RC network models are not apt for accurate representation of such dynamics. This paper investigates the suitability of a simple fractional order model for accurately representing such characteristics of the supercapacitors for pulse power applications. The identification of the fractional order model parameters from constant resistance charge/discharge test, constant current charge/discharge test and impedance spectroscopy is discussed. Based on the test results, the shortcomings of the simple fractional order model in representing the pulse power applications, owing to the variation of the fractional order model parameters are examined. An adaptive fractional order model considering the nonlinear voltage and frequency dependence on the parameters is then deduced. A procedure for identifying the model parameters is presented and the validity of the model is verified using various test profiles.

Cyclic Reservoir Computing with FPGA Devices for Efficient Channel Equalization

Abstract: The reservoir computation (RC) is a recurrent neural network architecture that is very suitable for time series prediction tasks. Its implementation in specific hardware can be very useful in relation to software approaches, especially when low consumption is an essential requirement. However, the hardware realization of RC systems is expensive in terms of circuit area and power dissipation, mainly due to the need of a large number of multipliers at the synapses. In this paper, we present an implementation of an RC network with cyclic topology (simple cyclic reservoir) in which we limit the available synapses’ weights, which makes it possible to replace the multiplications with simple addition operations. This design is evaluated to implement the equalization of a non-linear communication channel, and allows significant savings in terms of hardware resources, presenting an accuracy comparable to previous works.

A 0.7V Fully-on-Chip Pseudo-Digital LDO Regulator with 6.3μA Quiescent Current and 100mV Dropout Voltage in 0.18-μm CMOS

Abstract: This paper presents an NMOS pseudo-digital low-dropout (PD-LDO) regulator that supports low-voltage operation by eliminating the amplifier of an analog LDO. The proposed pseudo-digital control loop consists of a latched comparator, a 2X charge pump and a RC network. It detects the output voltage and provides a continuous gate control signal for the power transistor by charging and discharging the RC network. Fast transient response is achieved due to the source follower structure of the power NMOS, with a small output capacitor and small occupied chip area and without consuming large quiescent current. The proof-of-concept design of the proposed PD-LDO is implemented in a 0.18-J.1m CMOS process. The minimum supply voltage is 0.7 V, with a dropout voltage of 100 mV and a maximum load current of 100 mA. Using only 20 pF of on-chip output capacitor and 10 MHz comparator clock frequency, the undershoot is 106 mV with 90 mA load current step and 150 ns edge time. The quiescent current is only 6.3 μA and the active chip area is 0.08 mm2.

CMOS-Based Multifrequency Impedance Analyzer for Biomedical Applications

Abstract: In this paper, we present a monolithic microsystem, which can perform bioimpedance analysis and electroimpedance tomography measurements as well as record electrocardiogram signals In contrast to a full analog lock-in approach, a mixed analog/digital solution is adopted The proposed solution has been designed, implemented, and tested using a commercial 035-μm CMOS technology The tuning range of the signal generator and the detector is from 10 kHz to 10 MHz in 1 kHz steps The circuit ensures a CMRR of 81 dB@10 kHz, which increases to 84 dB@10 MHz The measured equivalent input noise power spectral density is en = 257 nV/√Hz at 10 kHz in the worst case, close to the 1/f corner frequency It decreases until en = 18 nV/√Hz at 1 MHz and en = 19 nV/√Hz at 10 MHz Measurements of a reference RC network performed with the proposed monolithic solution and compared with a Keysight E4980A Precision LCR Meter shows a maximal relative error of 08% over the whole operating frequency range

Optimization of the two-stage common-emitter transistor amplifier for equalization circuit in visible light communication system

Abstract: The equalization circuit in the visible light communication (VLC) system has large impacts on the frequency response and can greatly improve the 3-dB modulation bandwidth The optimization of the two-stage common-emitter transistor amplifier for equalization circuit is presented in detail and the design rules are disclosed At first, the frequency response of the single-stage amplifier is derived and the simulated characteristic curves illustrated the changing regularity of four main factors are given Subsequently, the frequency response of the two-stage amplifier is investigated by simulation It is shown that the capacitors in the resistance–capacitance (RC) network has large impacts on the low-frequency range, while the resistors in the RC network can adjust the high-frequency, and the resistors in the emitter can adjust the low-frequency Experimental measurements of the fabricated equalization circuit demonstrated the simulation results Then, the two-stage amplifier is induced as post-equalization circuit (post-EQC) or pre-equalization circuit (pre-EQC) and the measured frequency response curves are given The equalization circuit with proper sets of capacitors and resistors would flatten the frequency response curve of the VLC system It is shown that the 3-dB modulation bandwidth of the VLC system equipped with post-EQC or pre-EQC can be expanded to 292 MHz or 304 MHz, respectively Moreover, if the photoelectric receiver and the post-EQC are combined in the optimization, the 3-dB modulation bandwidth can be expanded to 375 MHz

A low-cost, low-power, 10MHz multifrequency impedance analyzer

Abstract: In this paper we present a low-cost low-power multifrequency impedance analyzer based on a monolithic mixed-signal (analog/digital) microchip that performs all the tasks necessary to perform impedance measurements in the frequency range from 10kHz to 10MHz. In contrast to a full analog lock-in approach, this mixed-signal solution combines the lock-in approach with the dual step super-heterodyne demodulation scheme. The circuit ensures a CMRR of 81dB@10kHz, which increases to 84dB@10MHz. The measured equivalent input noise power spectral density is e n =2.57nV/√Hz at 10kHz in the worst case, close to the 1/f corner frequency. It decreases to e n =1.8nV/√Hz at 1MHz and e n =1.9nV/√Hz at 10MHz. Measurements of a reference RC network performed with the proposed low-cost low-power multifrequency impedance analyzer are compared with a Keysight E4980A Precision LCR Meter showing a maximal relative error of 0.8% over the whole operating frequency range.

Megawatt-grade broadband impedance measuring apparatus based on MMC, and control method thereof

Abstract: The invention discloses a megawatt-grade broadband impedance measuring apparatus based on MMC, and a control method thereof. The impedance measuring apparatus includes a current disturbance injectionunit, wherein the current disturbance injection unit includes an MMC converter and an isolation branch circuit which is connected with the MMC converter; each phase half-bridge arm of the MMC converter includes one reactor and four sub modules in series; the reactor is connected with the sub modules in series; the isolation branch unit includes a Y-Y type isolation transformer with respective phase change ratio 1; the auxiliary edge of the Y-Y type isolation transformer is connected with an RC circuit in parallel; and each phase original edge of the Y-Y type isolation transformer is connectedwith the corresponding phase bridge arm of the MMC converter. The megawatt-grade broadband impedance measuring apparatus based on MMC satisfies the refinement requirement of a generating equipment simulation model in a new energy generating base, and fills the gap on an accurate measuring method and equipment for high voltage, megawatt-grade and broadband impedance characteristic.

Data-Driven Identification of a Thermal Network in Multi-Zone Building

Abstract: System identification of smart buildings is necessary for their optimal control and application in demand response. The thermal response of a building around an operating point can be modeled using a network of interconnected resistors with capacitors at each node/zone called RC network. The development of the RC network involves two phases: obtaining the network topology, and estimating thermal resistances and capacitance's. In this article, we present a provable method to reconstruct the interaction topology of thermal zones of a building solely from temperature measurements. We demonstrate that our learning algorithm accurately reconstructs the interaction topology for a 5 zone office building in EnergyPlus with real-world conditions. We show that our learning algorithm is able to recover the network structure in scenarios where prior research prove insufficient.