Showing papers on "RC circuit published in 2019"

Synthesis and Optimization of Fractional-Order Elements Using a Genetic Algorithm

Abstract: This study proposes a new approach for the optimization of phase and magnitude responses of fractional-order capacitive and inductive elements based on the mixed integer-order genetic algorithm (GA), over a bandwidth of four-decade, and operating up to 1 GHz with a low phase error of approximately ±1°. It provides a phase optimization in the desired bandwidth with minimal branch number and avoids the use of negative component values, and any complex mathematical analysis. Standardized, IEC 60063 compliant commercially available passive component values are used; hence, no correction on passive elements is required. To the best knowledge of the authors, this approach is proposed for the first time in the literature. As validation, we present numerical simulations using MATLAB ® and experimental measurement results, in particular, the Foster-II and Valsa structures with five branches for precise and/or high-frequency applications. Indeed, the results demonstrate excellent performance and significant improvements over the Oustaloup approximation, the Valsa recursive algorithm, and the continued fraction expansion and the adaptability of the GA-based design with five different types of distributed RC/RL network.

A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range

Abstract: The controller of a current-mode buck converter is realized by only time-domain circuits such as voltage-controlled oscillator (VCO), voltage-controlled delay line (VCDL), and phase detector (PD). The inductor current is sensed by a VCO, which helps improving power efficiency and eliminates the need for the slope compensation preventing the sub-harmonic oscillation. The type-II frequency compensation network is realized by a combination of VCO and VCDL without an error amplifier (EA) and RC network which may consume large power and occupy large silicon area. Instead of voltage comparator, a PD detects the error of the output voltage, which allows the switching duty cycle and thus the output voltage to be controlled in a wide range. With the proposed time-domain current-mode controller, a buck converter has been implemented in a 65-nm CMOS process. The output voltage can be regulated from 0.15 to 1.69 V from a 1.8-V input and the maximum load current is 0.6 A. The peak power efficiency is 94.9% when the output is 1.5 V and the load current is 250 mA. The load transient speed is better than 3.5 $\mu \text{s}$ for both the step-up and step-down changes of the load current by 480 mA in 0.1 $\mu \text{s}$ .

A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor

Abstract: A current-mode hysteretic buck converter is described in which inductor current is sensed by a resistor-capacitor (RC) network. The inductor current sensing RC network is reset multiple times per switching clock period, which allows it to have time constant much smaller than switching clock period and therefore occupy small silicon area. A frequency regulator ensures the switching frequency to be constant regardless of the operating condition of the buck converter and also integrates comparator delay compensator as its loop filter. The current-mode hysteretic buck converter implemented in a 65 nm complementary metal-oxide-semiconductor (CMOS) process provides 0.6–2.0 V output from 3.3 V input with 1 MHz switching frequency. The maximum load current is 1.5 A and the measured peak power efficiency is 96.3%.

A Self-Tuned Class-E Power Oscillator

Abstract: The efficiency and output power of a high- $Q$ Class-E power amplifier (PA) are very sensitive to the values of the circuit components. Any mismatch between the nominal Class-E frequency and the input clock frequency could result in considerable degradation in the efficiency and much change in the output power. In this paper, we present a new self-oscillating Class-E PA, or so-called Class-E power oscillator (PO), whose feedback network is mainly constructed of a low- $Q$ RC circuit. As a result, the phase response of the feedback network is almost flat around the operating frequency, and if the nominal Class-E frequency of the load network changes due to variations in the component values, the phase shift in the feedback network does not change considerably, and therefore, the Class-E operation of the circuit is substantially maintained. We also present a complete design procedure for the proposed Class-E PO. We have built and tested a sample Class-E PO based on the proposed circuit. At $V_{DD}= {\text{4.5}}\,{\text{V}}$ , the measured oscillation frequency, output power, and efficiency of the circuit are 800 kHz, 0.96 W, and 89%, respectively. Simulation and measurement results confirmed that the efficiency and output power of the proposed Class-E PO have small sensitivities to the variations in the component values; therefore, we call the proposed circuit a self-tuned Class-E PO.

Jitter-Aware Target Impedance

Abstract: A new concept of target impedance which directly correlates the I/O buffer output jitter with the power distribution network (PDN) design is proposed. Jitter-ware target impedance is derived from the time domain waveform of power voltage ripple and the maximum allowable jitter assuming the single stage buffer as a RC network, which is then applied to the PDN design given a certain jitter specification. From HSPICE simulation of transient switching current, PDN impedance and power voltage ripple, it is shown that the proposed jitter-aware target impedance successfully correlates power supply induced jitter (PSIJ) and PDN impedance parameters with a simple analytical expression.

Integration of SMT-based Scheduling with RC Network Calculus Analysis in TTEthernet Networks

Abstract: In mixed-criticality Ethernet-based time-triggered networks, like TTEthernet, time-triggered communication (TT) coexists with rate-constrained (RC) and best-effort (BE) traffic. A global communication scheme, i.e., a schedule, establishes contention-free transmission times for TT flows ensuring guaranteed low latency and minimal jitter. Current approaches use Satisfiability Modulo Theories (SMT) to formulate the scheduling constraints and solve the resulting problem. However, these approaches do not take into consideration the impact of the TT schedule on RC traffic. Hence, the resulting TT schedule may cause the worst-case latency requirements of RC traffic not to be fulfilled anymore.In this paper, we present a novel method for including an RC analysis in state-of-the-art SMT-based schedule synthesis algorithms via a feedback loop in order to maintain the optimality properties of the SMT-based approaches while also being able to improve the RC traffic delays. Our method is designed in such a way that it can be readily integrated into existing SMT- or MiP-based solutions. We evaluate our approach using variants derived from a realistic use-case and present methods to further improve the efficiency of our feedback-based approach.

Role of Quasiparticles in an Electric Circuit with Josephson Junctions.

Abstract: Although Josephson junctions can be viewed as highly nonlinear impedances for superconducting quantum technologies, they also possess internal dynamics that may strongly affect their behavior. Here, we construct a computational framework that includes a microscopic description of the junction (full fledged treatment of both the superconducting condensate and the quasiparticles) in the presence of a surrounding electrical circuit. Our approach generalizes the standard resistor capacitor Josephson model to arbitrary junctions (including, e.g., multiterminal geometries and/or junctions that embed topological or magnetic elements) and arbitrary electric circuits treated at the classical level. By treating the superconducting condensate and quasiparticles on equal footings, we capture nonequilibrium phenomena such as multiple Andreev reflection. We show that the interplay between the quasiparticle dynamics and the electrical environment leads to the emergence of new phenomena. In a RC circuit connected to single channel Josephson junction, we find out-of-equilibrium current-phase relations that are strongly distorted with respect to the (almost sinusoidal) equilibrium one, revealing the presence of the high harmonic ac Josephson effect. In an RLC circuit connected to a junction, we find that the shape of the resonance is strongly modified by the quasiparticle dynamics: close to resonance, the current can be smaller than without the resonator. Our approach provides a route for the quantitative modeling of superconducting-based circuits.

Negative Group Delay Theory of a Four-Port RC-Network Feedback Operational Amplifier

Abstract: An innovative negative group delay (NGD) theory based on a unity direct chain feedback (UDCF) circuit topology is developed in this paper. This NGD circuit is an active cell constituted by an operational amplifier in feedback with a four-port RC-network. This NGD circuit theory is developed based on the S-parameter model analytically established from the equivalent impedance matrix. The UDCF group delay frequency response is expressed as a function of the feedback RC-cell and the operational amplifier parameters. The NGD analysis of the developed UDCF cell is introduced. According to theoretical analysis, under a certain condition, the UDCF topology is susceptible to behave as a low-pass NGD function. The UDCF cell NGD characteristics are defined theoretically. The theoretical prediction is verified numerically and experimentally in both the frequency- and time-domain by designing and fabricating an active PCB prototype. The simulations and experimentations show that the UDCF circuit exhibits an NGD of approximately -38 ns with NGD cut-off frequency of about 5.5 MHz. More importantly, it is demonstrated in the time-domain that the low-pass NGD effect enables the UDCF cell to generate advanced output with sinc waveform input voltages.

Relaxation digital-to-analogue converter

Abstract: The novel relaxation digital-to-analogue conversion technique, which takes advantage of the exponential impulse response of a first-order RC network to generate binary-weighted voltages, is proposed to design standard-cell based, mismatch-insensitive, ultra-low power, tiny digital-to-analogue converters targeting the requirements of Internet of Things applications. The effectiveness of the approach is validated by simulations and measurements performed on a proof-of-concept 10 bit, 300 S/s field programmable gate array prototype.

Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter-Wave Applications

Abstract: A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$ . The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications.

Shortcut to stationary regimes: A simple experimental demonstration

Abstract: We introduce an inverse engineering approach to drive an RC circuit. This technique is implemented experimentally (1) to reach a stationary regime associated with a sinusoidal driving voltage in a very short amount of time, (2) to ensure a fast discharge of the capacitor, and (3) to guarantee a fast change from one stationary regime to another driven at different frequencies. This work can be used as a simple experimental project dedicated to the computer control of a voltage source. Besides the specific example addressed here, the proposed method provides an original use of simple linear differential equations to control the dynamical quantities of a physical system and has therefore a certain pedagogical value.

Design and analysis of an LCC resonant converter for xenon flash lamp simmer circuit

Abstract: This paper presents a 2.5-kW (500 V/5 A) simmer circuit for a xenon flash lamp driver. The simmer circuit is based on an LCC resonant converter to take advantage of minimal arc energy from the current source characteristic. The output under no load condition was analyzed. The converter minimizes filter size with high switching frequency through the use of zero-voltage switching and SiC power devices. A gate driver with variable dead time to assist soft switching was designed. The design criteria of variable dead time implemented through a simple RC circuit are presented. A PSpice simulation was performed to verify the parameter design. The simmer circuit was implemented based on the designed LCC converter. The circuit was tested at a resistive load under rated conditions (500 V/5 A) and open condition (1400 V/0 A). The Xenon flash lamp driver was implemented using the developed simmer circuit and trigger circuit. The prototype was tested to maintain the lamp under various simmering current conditions. The influence of the arc energy on the reliability of the triggering operation was proven by comparing the waveform for filter capacitor values. The experimental results verify that the designed circuit can be effectively used for simmering xenon flash lamps.

Graphene–Si CMOS oscillators

Abstract: Graphene field-effect transistors (GFETs) offer a possibility of exploiting unique physical properties of graphene in realizing novel electronic circuits. However, graphene circuits often lack the voltage swing and switchability of Si complementary metal–oxide-semiconductor (CMOS) circuits, which are the main building block of modern electronics. Here we introduce graphene in Si CMOS circuits to exploit favorable electronic properties of both technologies and realize a new class of simple oscillators using only a GFET, Si CMOS D latch, and timing RC circuit. The operation of the two types of realized oscillators is based on the ambipolarity of graphene, i.e., the symmetry of the transfer curve of GFETs around the Dirac point. The ambipolarity of graphene also allowed to turn the oscillators into pulse-width modulators (with a duty cycle ratio ∼1 : 4) and voltage-controlled oscillators (with a frequency ratio ∼1 : 8) without any circuit modifications. The oscillation frequency was in the range from 4 kHz to 4 MHz and limited only by the external circuit connections, rather than components themselves. The demonstrated graphene–Si CMOS hybrid circuits pave the way to the more widespread adoption of graphene in electronics.

Potential distribution on the stress grading system of high voltage rotating machines — Part II transient measurements and simulation profiles

Abstract: The authors developed a system that utilizes a Pockels sensor to measure the potential distribution along the stress grading (SG) system of a form wound coil. Potential distributions on a bar coil under a 50 Hz sinusoidal wave, 1 kHz rectangular wave, 1 kHz repetitive impulse, and two level pulse width modulation (PWM) voltage were measured using this system. The results are discussed using an equivalent circuit of the bar coil, which consists of a distributed constant type RC circuit. Calculated potential distributions with this model were quantitatively consistent with the measured results. When the penetration length of the high frequency component of the applied voltage was shorter than the length of the corona armor tape (CAT), a high-potential gradient developed in the CAT while the low-frequency component transmitted to the stress grading tape (SGT) region. In addition, the electric field distribution and power dissipation in the SG system were computed based on the finite element method (FEM). It was evident from the computed results that a frequency component of more than 200 kHz had little influence on the power dissipation in the SGT in this system.

Signal compensation circuit of pipeline corrosion degree measuring instrument

Abstract: The invention discloses a signal compensation circuit of a pipeline corrosion degree measuring instrument. The signal compensation circuit comprises a frequency collecting circuit, a push-pull buffercircuit and a compensation output circuit; the frequency collecting circuit collects analog signal frequencies when the pipeline corrosion degree measuring instrument works; the push-pull buffer circuit applies a push-pull circuit composed of a triode Q3, a triode Q4, a triode Q5, a diode D4 and a diode D3 to process the signals, meanwhile applies a buffer circuit composed of a resistor R8, a capacitor C4 and a triode Q6 to buffer the signals, and applies a triode Q7 to feed operational amplifier AR1 output signals back to an emitting electrode of the triode Q5, finally, an operational amplifier AR2 amplifies the signals in a noninverting mode and then inputs the signals into the compensation output circuit, finally, the compensation output circuit applies a power supply +10 V and is subjected to pressure dividing through a variable resistor RW2 to compensate operational amplifier AR2 output signals, and applies a resistor R16, a resistor R17, a capacitor C5 and a capacitor C6 to constitute a RC circuit to filter the signals and then output the signals, and the analog signal frequencies can be converted to compensating signals of analog signals of the pipeline corrosion degree measuring instrument.

Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

Abstract: This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of $$\pm \,v_x \pm \,v_y$$ are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1 $$\%$$ for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 $$\upmu $$ W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 $$\upmu $$ m CMOS standard technology is used, showing a silicon area consumption of $$280\,\upmu \hbox {m} \times 400\,\upmu $$ m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.

Nonlinear Double-Capacitor Model for Rechargeable Batteries: Modeling, Identification and Validation

Abstract: This paper proposes a new equivalent circuit model for rechargeable batteries by modifying a double-capacitor model proposed in [1]. It is known that the original model can address the rate capacity effect and energy recovery effect inherent to batteries better than other models. However, it is a purely linear model and includes no representation of a battery's nonlinear phenomena. Hence, this work transforms the original model by introducing a nonlinear-mapping-based voltage source and a serial RC circuit. The modification is justified by an analogy with the single-particle model. Two parameter estimation approaches, termed 1.0 and 2.0, are designed for the new model to deal with the scenarios of constant-current and variable-current charging/discharging, respectively. In particular, the 2.0 approach proposes the notion of Wiener system identification based on maximum a posteriori estimation, which allows all the parameters to be estimated in one shot while overcoming the nonconvexity or local minima issue to obtain physically reasonable estimates. An extensive experimental evaluation shows that the proposed model offers excellent accuracy and predictive capability. A comparison against the Rint and Thevenin models further points to its superiority. With high fidelity and low mathematical complexity, this model is beneficial for various real-time battery management applications.

Experimental understanding of polarization switching in PZT ferroelectric capacitor

Abstract: In this study, the transient responses of polarization switching in a Pb(Zr0.52Ti0.48)O3 (PZT) ferroelectric capacitor are experimentally investigated. In order to measure the transient response of polarization switching in the ferroelectric capacitor, a conventional RC circuit consisting of a resistor and the PZT ferroelectric capacitor is first built. Then, to investigate the impact of the number of domains in the ferroelectric capacitor on the transient response, the three different sizes of top electrodes of the capacitor are chosen. The results show that the ferroelectric capacitor with a small-sized electrode is charged faster than the other capacitors with medium/large-sized electrodes. It is concluded that the number of domains affects the charging behavior, i.e., the ferroelectric capacitor is charged faster as the number of domains decreases. The effect of static terms (i.e., the alpha and beta parameters) on the transient responses is also studied. From the experimental data obtained above, the differential voltage amplification due to the polarization switching is observed. Using the multidomain Landau-Khalatnikov model, a circuit-level simulation is provided to support the experimental evidence. The simulation results show that the differential voltage amplification increases as the value of rho (ρ) coefficient decreases.

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

Abstract: In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide lower in-band noise than a bang-bang phase detector-based hybrid PLL (BB-HPLL). We also present noise analysis of the proposed PLL which shows that in-band noise can be further reduced by increasing the integral path gain, which is contrary to conventional design of BB-HPLLs where I path gain is minimized. A prototype chip fabricated in the 65-nm CMOS achieves 13-dB improvement of in-band phase noise compared to a conventional hybrid PLL and 2.08 psrms jitter at 4.8 GHz, while consuming 2.22 mW from a 1.0-V supply.

Identification of Li-ion Battery Model Parameters

Abstract: The paper describes Li-ion battery models and the possibility to identify its parameters. The battery model is considered as an equivalent RC circuit, which can with good accuracy describe short and long-term dynamic states of the battery. There is done some discussion about problems with the identification of individual parameters.

Fractional-Order Mihalas–Niebur Neuron Model Implementation Using Current-Mirrors

Abstract: A simple realization of the fractional-order Mihalas-Niebur neuron model is presented in this work. The required low-pass filter is implemented using current-mirrors offering simple circuitry and, also, electronic tunability of the realized time-constant. Due to the limited bandwidth required for this application, the necessary fractional-order capacitor is realized using an appropriately configured second-order RC network. The proposed realization highlights the connection between the fractional-order and the frequency spiking of the model through appropriate simulation results, which are derived via the Analog Design Environment of Cadence software, using MOS transistor models provided by the AMS $0.35\mu\mathrm{m}$ process.

A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing

Abstract: The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a V TH -tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.

Capacitance Measurements System Using RC Circuit

Abstract: .

A charge amplifier with noise peaking suppression and gain drop compensation utilizing a Quasi-Miller RC network

Abstract: A charge amplifier with noise peaking suppression and gain drop compensation is proposed. By utilizing the proposed Quasi-Miller RC network, the noise peaking is suppressed and gain drop is compensated, which alleviates the design trade-off between charge gain and output root-mean-square (RMS) noise, therefore obtains an improved sensitivity. Meanwhile, the Quasi-Miller RC network permits the charge amplifier to support ultra-low frequency operation without using a huge resistor, which is normally required by the charge amplifier. The fabricated charge amplifier demonstrates an input-referred RMS noise charge of 909 aC, a charge gain of 10.2 V/pC and a 3-dB bandwidth from 80 Hz to 38 MHz. Low noise and high charge gain are obtained simultaneously. Meanwhile, extremely low cut-off frequency is also obtained, which is beneficial to maintain the signal integrity.

Valley and peak detection for switching power converter

Abstract: A switching power converter is provided with a phase-shifting RC network for phase-shifting a divided version of a drain voltage of a power switch transistor into a phase-shifted voltage. A comparator compares the phase-shifted voltage to a DC bias voltage to detect peaks and valleys during resonant oscillations of the drain voltage of the power switch transistor.

Junction Temperature Estimation Based on Updating RC Network for Different Liquid Cooling Conditions

Abstract: The failure of power converters and inverters due to thermal stress can threaten the safety and reliability of electrical vehicles (EVs). Junction temperature estimation for power devices is the key factor to maintain safe operation and to extend power device lifetime. This paper proposes a detailed transient Foster thermal model with updating RC parameters at 216 cooling conditions based on coolant flowrate (5L/min to 10.5L/min) and coolant temperature (5°C to 90°C) since the liquid coolant is the major heat dissipating path in the module. The vehicle controller can store and keep updating these 216 RC values based on the coolant temperature and coolant flowrate measurements to provide accurate online IGBT junction temperature estimation. Test data from supplier is used to validate the model at selected operating points.

Diagnostic Technique for Electrical Tree by Current Integration Method

Abstract: The degradation of insulating property of polymeric materials was evaluated by the new diagnostic technique of current integration system, hereafter referred to as the “Q(t)-meter”. The Q(t)-meter measures the change with time in integrated charge accumulated by a capacitor inserted between a DC high-voltage power supply and a sample of the insulation material under study. Q(t)-meter is suitable for the monitoring of time dependence of leakage current of the insulating sample under DC voltage. To demonstrate the performance of this new device, we evaluated the influence of generation and propagation of “electrical tree” in epoxy resin sample on DC leakage current. The electrical tree is a typical electrical degradation of polymeric materials. Hence, nondestructive diagnostic methods for electrical tree are expected. In this study, the electrical tree was generated in the epoxy resin by AC high voltage between two needle electrodes. The interelectrode distance was 2 mm. In the Q(t) measurement, the sampling frequency, total sampling time, DC applied time, and test voltages were 2 s, 600 s, 900 s, 250-1,000 V, respectively. We conducted Q(t) measurement at three stages of electrical treeing - before tree generation, after tree generation, and after tree propagation. It was found that the leakage current increased with increase in the tree length. A remarkable trend of steep rise and fall in the Q(t) curve was also observed. Experimental results obtained by the Q(t)-meter were analyzed assuming an “RC circuit model”.