RC circuit

About: RC circuit is a research topic. Over the lifetime, 5824 publications have been published within this topic receiving 62152 citations. The topic is also known as: resistor–capacitor circuit & RC filter.

Circuit for electrostatic discharge protection

Abstract: A circuit (100) ensures electrostatic discharge (ESD) protection during an ESD event. The ESD circuit (100) has a current shunting device (135), a RC trigger circuit (125) and a RC delay circuit (130). The shunting device (135) is connected between two IC power supply rails, and provides the primary current path for a positive ESD event referenced from one power supply rail (V DD 105) to the other (V ss 110). The trigger circuit (125) initially activates the shunting device into a low resistance conductive state in response to an ESD event. The RC delay circuit (130) serves to maintain the shunting device in the conductive state, initially produced by the trigger circuit (125), for the remaining duration of the ESD event. A large capacitor required to achieve the delay time in this RC circuit may be eliminated by utilizing the gate-to-body capacitance in the existing shunting device (135).

Applicability of Metal/Insulator/Metal (MIM) Diodes to Solar Rectennas

Abstract: The current-voltage (I-V) characteristics of metal/insulator/metal (MIM) diodes illuminated at optical frequencies are modeled using a semiclassical approach that accounts for the photon energy of the radiation. Instead of classical small-signal rectification, in which a continuous span of the dc I-V curve is sampled during rectification, at optical frequencies, the radiation samples the dc I-V curve at discrete voltage steps separated by the photon energy (divided by the electronic charge). As a result, the diode resistance and responsivity differ from their classical values. At optical frequencies, a diode with even a moderate forward-to-reverse current asymmetry exhibits high quantum efficiency. An analysis is carried out to determine the requirements imposed by the operating frequency on the circuit parameters of antenna-coupled diode rectifiers, which are also called rectennas. Diodes with low resistance and capacitance are required for the RC time constant of the rectenna to be smaller than the reciprocal of the operating frequency and to couple energy efficiently from the antenna. Existing MIM diodes do not meet the requirements to operate efficiently at visible-to-near-infrared wavelengths.

Performance computation for precharacterized CMOS gates with RC loads

Abstract: For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure. The delay and power are calculated with errors on the same order as those for the original empirical equations. Moreover, a linear equivalent gate model is generated which accurately captures the delays at the interconnect fan-out nodes.

Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters

Abstract: This paper describes a new MOS resistive circuit containing four matched MOS transistors. It allows to fully integrate known active RC filter structures on a single chip without externals components. Integrator, summer and lossy integrator circuits with a single operational amplifier are shown. The new circuits improve on previously suggested MOS active filters.

Efficient coupled noise estimation for on-chip interconnects

Abstract: Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.