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Reconfigurable computing

About: Reconfigurable computing is a(n) research topic. Over the lifetime, 7854 publication(s) have been published within this topic receiving 126057 citation(s).

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Papers
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Open accessJournal ArticleDOI: 10.1145/508352.508353
Katherine Compton1, Scott Hauck2Institutions (2)
Abstract: Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

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  • Fig. 1 . A programming bit for SRAM-based FPGAs [Xilinx 1994] (left) and a programmable routing connection (right).
    Fig. 1 . A programming bit for SRAM-based FPGAs [Xilinx 1994] (left) and a programmable routing connection (right).
  • Fig. 2 . D flip-flop with optional bypass (left) and a 3-input LUT (right).
    Fig. 2 . D flip-flop with optional bypass (left) and a 3-input LUT (right).
  • Fig. 3 . Different levels of coupling in a reconfigurable system. Reconfigurable logic is shaded.
    Fig. 3 . Different levels of coupling in a reconfigurable system. Reconfigurable logic is shaded.
  • Fig. 4 . A basic logic block, with a 4-input LUT, carry chain, and a D-type flip-flop with bypass.
    Fig. 4 . A basic logic block, with a 4-input LUT, carry chain, and a D-type flip-flop with bypass.
  • Fig. 5 . A generic island-style FPGA routing architecture.
    Fig. 5 . A generic island-style FPGA routing architecture.
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Topics: Reconfigurable computing (68%), PipeRench (64%), FpgaC (62%) ...read more

1,643 Citations


Open accessBook
31 Mar 1999-
Abstract: From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert.

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Topics: FPGA prototype (62%), Reconfigurable computing (55%), CAD (51%)

1,309 Citations


Proceedings ArticleDOI: 10.1109/FPGA.1997.624600
Jay Hauser1, John Wawrzynek1Institutions (1)
16 Apr 1997-
Abstract: Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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Topics: Reconfigurable computing (63%), PipeRench (56%), UltraSPARC (54%) ...read more

1,020 Citations


Journal ArticleDOI: 10.1109/12.859540
H. Singh1, Ming-Hau Lee1, Guangming Lu1, Fadi J. Kurdahi1  +2 moreInstitutions (2)
Abstract: This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.

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Topics: Reconfigurable computing (59%), Processor array (55%), SIMD (51%) ...read more

874 Citations


Open accessJournal ArticleDOI: 10.1145/2996868
Andrew Putnam1, Adrian M. Caulfield1, Eric S. Chung1, Derek Chiou2  +19 moreInstitutions (8)
Abstract: Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost It is challenging to improve all of these factors simultaneously To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA) Each server in the fabric contains one FPGA, and all FPGAs within a 48-server rack are interconnected over a low-latency, high-bandwidth networkWe describe a medium-scale deployment of this fabric on a bed of 1632 servers, and measure its effectiveness in accelerating the ranking component of the Bing web search engine We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system Under high load, the large-scale reconfigurable fabric improves the ranking throughput of each server by 95% at a desirable latency distribution or reduces tail latency by 29% at a fixed throughput In other words, the reconfigurable fabric enables the same throughput using only half the number of servers

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  • Figure 1: (a) A block diagram of the FPGA board. (b) A picture of the manufactured board. (c) A diagram of the 1 U, half-width server that hosts the FPGA board. The air flows from the left to the right, leaving the FPGA in the exhaust of both CPUs.
    Figure 1: (a) A block diagram of the FPGA board. (b) A picture of the manufactured board. (c) A diagram of the 1 U, half-width server that hosts the FPGA board. The air flows from the left to the right, leaving the FPGA in the exhaust of both CPUs.
  • Figure 2: The logical mapping of the torus network, and the physical wiring on a pod of 2 x 24 servers.
    Figure 2: The logical mapping of the torus network, and the physical wiring on a pod of 2 x 24 servers.
  • Figure 3: Components of the Shell Architecture.
    Figure 3: Components of the Shell Architecture.
  • Figure 4: Cumulative distribution of compressed document sizes. Nearly all compressed documents are 64 KB or less.
    Figure 4: Cumulative distribution of compressed document sizes. Nearly all compressed documents are 64 KB or less.
  • Figure 5: Mapping of ranking roles to FPGAs on the reconfigurable fabric.
    Figure 5: Mapping of ranking roles to FPGAs on the reconfigurable fabric.
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Topics: Reconfigurable computing (61%), Server (57%), Throughput (business) (53%)

747 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20221
2021110
2020158
2019168
2018178
2017252

Top Attributes

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Topic's top 5 most impactful authors

Wayne Luk

110 papers, 2.4K citations

Jürgen Becker

66 papers, 1.3K citations

Marco Platzner

36 papers, 729 citations

Iouliia Skliarova

30 papers, 365 citations

Michael Hübner

30 papers, 686 citations

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