Showing papers on "Reconfigurable computing published in 1990"

Third-generation architecture boosts speed and density of field-programmable gate arrays

Abstract: Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices. The architecture was devised to allow complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. This architecture is described. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices. >

Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine

Abstract: Tabula Rasa is a user reconfigurable hardware system under development in AT&T Bell Labs. Its purpose is to assist in the development of new hardware systems, and possibly to serve as a computing engine in its own right. The core of the system is a full-custom CMOS chip. This chip has electrically programmed logic and routing, and allows an external monitor to observe, control, and reconfigure the circuit during operation. Unlike currently available programmable logic devices this chip is targeted specifically at the development rather than the production environment. One or more of these chips could be wired into the development version of an application system, to add flexibility and simplify the design process by making the design more controllable and observable. In another type of application, an array of these chips could be assembled into a dedicated processor attached to a workstation. The architecture of the chip, some of the tradeoffs involved, and the CAD challenges needed to support it are outlined. >

System development using Actel field programmable gate arrays

Abstract: A new way to reduce risk and time in system-level development while retaining a high level of logic integration lies in the use of field-programmable gate arrays (FPGAs). An FPGA is an application-specific IC (ASIC) that is configurable by the designer at his or her desk. FPGAs are one-time programmable devices that are developed using a standard computer-aided-engineering (CAE) system and Actel software. As in any technology, a design is captured and functionality simulated. After the net list is translated and package pins assigned, the design must be mapped to the physical device and a file for programming the device must be created. The use of FPGAs provides benefits during all the stages of development. During prototyping the devices provide working hardware rapidly without the cost and delay of wire-wrapped standard device technology, whether for a prototype or emulation of masked gate arrays. Software development can begin as soon as a device is programmed. The design of a simple microprocessor-based computer system is considered as an example of how FPGAs can be used throughout the development cycle. >

Reconfigurable architecture for real-time 3-D parameter estimation from image sequences

Abstract: In this paper a multiprocessor architecture is proposed which is capable of handling real-time parameter estimation algorithms for estimating 3D body parameters from 2D image sequences. The implicit parallelism of the algorithm is used to obtain a highly efficient architecture while retaining modularity and flexibility. CONTENTS© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Field programmable gate arrays get enough speed and density for computer applications

Abstract: At the time of their introduction in 1985, field-programmable gate arrays (FPGAs) offered limited speed and logic density. Subsequent advances in architecture and process have resulted in major improvements in speed and logic density. Projections for further improvements in speed, density, and cost can be developed on the basis of anticipated improvements in architectures and process. These advances will result in a narrowing of the differences between conventional custom gate arrays and FPGAs. The topics covered are evolution of FPGA architectures, process advances for FPGAs, speed, density, cost, software, markets, and applications. >

Assessment of reconfiguring algorithms for MIMD architectures

Abstract: Some issues of reconfigurable computing systems with MIMD architecture are considered. A number of reconfiguring algorithms are analyzed by simulation from the aspect of the attainable fault tolerance.