Showing papers on "Reconfigurable computing published in 1992"

Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor

Abstract: An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.

Method and apparatus for debugging reconfigurable emulation systems

Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Field-Programmable Gate Arrays

Abstract: Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.

An efficient logic emulation system

Abstract: The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. The interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds or thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 XC3090 FPGAs for logic. A 32-b CPU datapath has been automatically realized and operated at speed, and demonstrates very good FPGA utilization. >

AnyBoard: an FPGA-based, reconfigurable system

Abstract: AnyBoard, a low-cost, field programmable gate array (FPGA)-based, reconfigurable rapid-prototyping system is described. The system hardware organization and software tools that help users automatically map designs to the FPGAs and manage the design process are discussed. The implementation of a pattern generator design is presented to illustrate the system's effectiveness. >

An adaptive machine architecture and compiler for dynamic processor reconfigurations

Abstract: Many computationally intensive tasks spend nearly all of their execution time within a small fraction of the executable code. Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to these frequently accessed portions. A method is presented which improves the performance of many computationally intensive tasks by utilizing information extracted at compile-time to synthesize new operations which augment the functionality of a core processor. By integrating adaptation into a general-purpose computer, one not only can reap the performance benefits of application-specific processors, but also retain the general-purpose nature by accommodating a wide variety of tasks. The newly synthesized operations are targeted to RAM-based logic devices which provide a mechanism for fast processor reconfiguration. A proof-of-concept system called PLADO, consisting of a specialized C configuration compiler, and a reconfigurable hardware platform is presented. Compilation and performance results are provided which confirm the concept viability, and demonstrate significant speed-up over conventional general-purpose architectures.

Fuzzy controller on FPGA chip

Abstract: A hardware implementation of fuzzy controllers on field programmable gate arrays (FPGAs) is described. FPGAs are semicustom integrated circuits that combine the attractive features of both programmable logic devices and gate arrays. Software for synthesizing fuzzy controllers into Boolean equations was developed. The file that contains the set of Boolean equations is accepted directly by the development system of the FPGA. The development system then produces the necessary code for programming the FPGA chip. The speed of the fuzzy controller is determined by the response time of the FPGA circuit that realizes the Boolean equations. A speed of 50M FLIPS was achieved. The software together with the FPGA development system provide a complete design automation tool for fuzzy controllers. >

Design of RM-nc: a reconfigurable neurocomputer for massively parallel-pipelined computations

Abstract: The design of RM-nc, a reconfigurable machine for massively parallel-pipelined computations, is considered with the objective of demonstrating that a completely reconfigurable platform, not only in the domain of communication and control but also in the domain of processing elements (PEs), is feasible. The implementation of a fast computational element and control environment for neural network simulations is presented in order to assess the cost of providing reconfigurability at computational level. The implementation of a fast floating-point sum-of-products circuit using special carry-save multipliers and extensive pipelining is outlined on a field programmable gate array (FPGA) platform. It is shown that the flexibility of FPGA devices can contribute to achieving good time/hardware performance when far less complex neurons are sufficient for simulation of a given neural network model. >

Reconfigurable special purpose hardware for scientific computation and simulation

Abstract: Xilinx Field Programmable Gate Arrays (FPGAs) are used to implement reconfigurable special purpose computing hardware for computationally intensive many-body problems in physics and mathematics. The inexpensive PC-based design environment used for this work is described, and the performance for several different problems of the resulting reconfigurable hardware is compared with that of some general purpose computers. The merits of using FPGAs in special purpose computational hardware are outlined.

Mapping division algorithms to field programmable gate arrays

Abstract: The mapping of a fundamental arithmetic operation, division, to the Xilinx XC4010, a lookup-table based FPGA (field-programmable gate array) is examined. It is shown how steps within the division algorithm can be merged by utilizing FPGAs and how parallelism can be exploited for optimal-performance FPGA implementations. Some mapping tradeoffs to reduce either the delay or the required number of logic blocks are shown. >

Reconfigurable logic: technology and applications

Abstract: Field programmable gate arrays (FPGAs) have the potential to revolutionise the design of modern computer systems. With the current generation of reconfigurable arrays, the distinction between hardware, software and firmware blurs, permitting the designer to mix and match according to application. The promise of logic systems that can be configured in fractions of a second holds out the very real possibility of designing adaptive hardware—machines that can optimise themselves for their environment. This article introduces the internal design of an ultra-fine grain FPGA family, the Plessey/Pilkington ERA, and briefly compares this with other families. The integrated design synthesis for mixed hardware/software systems is discussed and the article concludes with two examples of FPGA systems.

New application of FPGAs to programmable digital communication circuits

Abstract: This paper proposes a new design method to construct flexible, high performance digital communication systems. The method, called Amphibious Logic, combines top-down design with high level synthesis and reconfigurable hardware. The method's capability and problems that had to be solved associated are discussed. Design examples using the high level CAD system called PARTHENON and conventional FPGAs are illustrated. The results show that it is possible to create programmable, high performance digital communication circuits with the proposed method.

Reconfigurable machine and its application to logic diagnosis

Abstract: In this paper, we present a Reconfigurable Machine (RM). Its highly flexible architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a performance comparable to existing "special-purpose" engines. A Reconfigurable Machine Prototype (RMP) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RMP has been applied to logic diagnosis and logic simulator. The concept of RM may be the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high- level synthesis.

A System for Behavior Extraction from FPGA Implementations of Synchronous Designs

Abstract: The paper presents a system for extracting behavioral representations from FPGA (Field Programmable Gate Array) implementations of synchronous sequential designs. Behavior extraction offers advantages in the areas of simulation, verification, optimization and technology migration. A generic FPGA architecture has been defined. Necessary parameters can be specified to derive the desired architecture. The architecture details and the fuse-map describing the design implementation, form the inputs to the system. The behavior is extracted at two levels of abstractions , 1. boolean equations for the combinational logic and 2. finite-state-machine. The overall extraction flow with details of the different steps in the flow are presented. The results for six designs are presented. They clearly demonstrate the importance and usefulness of behavior extraction, especially for technology migration from FPGAs to the mask programmable gate arrays.

Mixed-Mode Multicomputers with Load Adaptability

Abstract: Dynamically reconfigurable mixed-mode computers are those systems that can be configured at run-time into Multiple SIMD and MIMD autonomous submachines Therefore, they are also known as MSIMD/MIMD computers In the existing MSIMD/MIMD architectures, the role of a processor to run as either a processing element “PE” or a control unit “CU”, is fixed at design time It will be shown that such static assignment adversely affects the system's flexibility and performance This paper introduces an MSIMD/MIMD architecture with dynamic processors assignments Unlike the existing machines, this architecture dynamically configures/reconfigures each processor to run as either a PE or a CU as needed A cost-efficient dynamically reconfigurable hardware is provided in order to establish a broadcasting link between any CU and its PEs in an SIMD submachine It will be shown that the proposed architecture offers significantly better performance/cost ratio than the existing comparables

A hardware prototyping board for complex digital design

Abstract: Logic simulation is not a satisfactory tool to verify a digital design as it offers no interaction with the complete system. A hardware prototyping board which can be programmed in minutes and can be plugged into a system immediately is described. The board contains four field-programmable gate arrays (FPGAs) equivalent to 16000 gates. Implementation is fully automated through a specially designed development system. Both the hardware board and the software can be reconfigured to use more FPGAs, offering a higher capacity prototyping system. >