Showing papers on "Reconfigurable computing published in 1998"

The roles of FPGAs in reprogrammable systems

Abstract: Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.

An integrated processor and programmable data path chip for reconfigurable computing

Abstract: The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable "hard-wired" functions.

The design and implementation of a context switching FPGA

Abstract: Dynamic reconfiguration of field programmable gate arrays (FPGAs) has recently emerged as the next step in reconfigurable computing. Sanders, A Lockheed Martin Company, is developing the enabling technology to exploit dynamic reconfiguration. The device being developed is capable of storing four configurations on-chip and switching between them on a clock cycle basis. Configurations can be loaded while other contexts are active. A powerful cross-context data sharing mechanism has been implemented. The current status of this work and future work are described.

System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

Abstract: A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

A quantitative analysis of reconfigurable coprocessors for multimedia applications

Abstract: Recently, computer architectures that combine a reconfigurable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of fine grain parallelism in applications. In this paper, we study the performance of the reconfigurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (FPGA) based reconfigurable coprocessor with the array processor called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC uses a 16-bit simple processor that is much larger than a Configurable Logic Block (CLB) of an FPGA. We have developed a simulator, a programming environment, and multimedia application programs to evaluate the performance of the two coprocessor architectures. The simulation results show that REMARC achieves speedups ranging from a factor of 2.3 to 7.3 on these applications. The FPGA coprocessor achieves similar performance improvements. However, the FPGA coprocessor needs more hardware area to achieve the same performance improvement as REMARC.

A method of designing fpgas for dynamically reconfigurable computing

Abstract: A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

The NAPA adaptive processing architecture

Abstract: The National Adaptive Processing Architecture (NAPA) is a major effort to integrate the resources needed to develop teraops class computing systems based on the principles of adaptive computing. The primary goals for this effort include: (1) the development of an example NAPA component which achieves an order of magnitude cost/performance improvement compared to traditional FPGA based systems, (2) the creation of a rich but effective application development environment for NAPA systems based on the ideas of compile time functional partitioning and (3) significantly improve the base infrastructure for effective research in reconfigurable computing. This paper emphasizes the technical aspects of the architecture to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals.

Converification system and method

Abstract: The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device. The user may decide to use actual I/O devices as well as modeled I/O devices in one debug session. The software clock is used as the external clock source for the target system and the external I/O devices to synchronize all data that is delivered between the coverification system and the external interface. The coverification system contains a control logic that provides traffic control between: (1) the RCC computing system and the RCC hardware array, and (2) the external interface (which are coupled to the target system and the external I/O devices) and the RCC hardware array. Because the RCC computing system has the model of the entire design in software, including that portion of the user design modeled in the RCC hardware array, the RCC computing system must also have access to all data that passes between the external interface and the RCC hardware array. The control logic ensures that the RCC computing system has access to these data. Pointers are used to latch data from the RCC computing system and the external interface to the internal nodes of the hardware model in the RCC hardware array. Pointers are also used to deliver data from the internal nodes of the hardware model to the RCC computing system and the external interface. Even if the data from the internal nodes of the hardware model is intended for the external interface, the RCC computing system must also be able to access this data as well.

A re-evaluation of the practicality of floating-point operations on FPGAs

Abstract: The use of reconfigurable hardware to perform high precision operations such as IEEE floating point operations has been limited in the past by FPGA resources. We discuss the implementation of IEEE single precision floating-point multiplication and addition. Then, we assess the practical implications of using these operations in the Xilinx 4000 series FPGAs considering densities available now and scheduled for the near future. For each operation, we present space requirements and performance information. This is followed by a discussion of an algorithm, matrix multiplication, based on these operations, which achieves performance comparable to conventional microprocessors. Algorithm implementation options and their performance implications are discussed and corresponding measured results are given.

Simulation server system and method

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.

Virtual logic system for reconfigurable hardware

Abstract: A set of reconfigurable hardware includes a number of field programmable gate arrays (FPGAs), a controller referred to as a page manager, and a RAM-based local memory. In an illustrative embodiment, each of the FPGAs is suitable for implementing any one of a number of different portions of a logic circuit. A netlist or other descriptive information characterizing the logic circuit is partitioned into a number of pages, each of the pages corresponding to one of the portions of the circuit. The page manager controls the loading and unloading of the pages from the local memory into the FPGAs of the reconfigurable hardware, and controls storage and transfer of inter-page signals. The page manager is configured to detect "page faults" such as, for example, an unloaded page with a full input buffer. The page manager responds to a given page fault by subsequently loading the previously unloaded page into one of the FPGAs. The page manager may include FIFO input buffers or other suitable sets of registers for storing inter-page signal values for loaded and unloaded pages.

Configuration compression for the Xilinx XC6200 FPGA

Abstract: One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system This overhead limits the speedups possible in this exciting new paradigm In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration

Managing pipeline-reconfigurable FPGAs

Abstract: While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

The flexibility of configurable computing

Abstract: There has been growing recent interest in configurable computing, which can be viewed as a hybrid between ASICs and programmable processors Configurable computing machines are implemented with programmable logic: flexible hardware that can be structured to fit the natural organization and data flow of a computation The enabling device for configurable computing is the field-programmable array (FPGA) For applications characterized by deeply pipelined, highly parallel, and integer arithmetic processing, configurable computing machines can outperform alternative solutions by up to an order of magnitude The combination in a single device of dedicated hardware and rapid, submillisecond-scale reprogrammability constitutes an exciting and promising development whose implications are only just beginning to be exploited We begin with a brief tutorial on FPGAs that describes the most common FPGA architectures and how these architectures are used to support computation, memory access, and data flow We then present FPGAs as computing machines and focus on devices that are reconfigured during run time Ongoing research involving FPGAs and future directions are also discussed

Testing configurable LUT-based FPGA's

Abstract: We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

The Future of Reconfigurable Systems

Abstract: In the decade since FPGAs were invented they have created many new opportunities. Perhaps the most exciting is reconfigurable computing. In this paper we present a vision of the next decade of reconfigurable computing. FPGA architectures will support millions of gates on a chip, requiring the integration of FPGAs with CPUs, DSPs, and SRAMs. Reconfigurable computing specific architectural features will be developed, though their place in the commercial marketplace must be carefully considered. CAD support for reconfigurable system, and commercial applications of reconfigurable computing, will be major keys to deploying reconfigurable computing devices into the mainstream. Finally, we can consider applying the lessons of Run-Time-Reconfiguration within ASIC designs. Hopefully, these technologies can help create a commercial market for reconfigurable computing, making it a truly general-purpose paradigm.

Compiling system and method for partially reconfigurable computing

Abstract: A compiling system and method generates a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations. A compiler selectively compiles high-level source code statements for execution using configurations of the reconfigurable portion of the processing unit responsive to meta-syntax compiler directives. A linker creates object files that optionally encapsulate bitstreams specifying hardware organizations corresponding to the configurations.

An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures

Abstract: This paper presents an integrated design system called SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAS). The SPARCS system accepts design specifications at the behavior level, in the form of task graphs. The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the reconfigurable architecture, a spatial partitioning tool to map the tasks to individual FPGAs, and a high-level synthesis tool to synthesize efficient register-transfer level designs for each set of tasks destined to be downloaded on each FPGA. Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each FPGA design segment. A distinguishing feature of the SPARCS system is the tight integration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. This paper presents an overview of SPARCS and the various algorithms used in the system, along with a brief description of how a JPEG-like image compression algorithm is mapped to a Multi-FPGA board using SPARCS.

Instruction-Level Parallelism for Reconfigurable Computing

Abstract: Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP) In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language

Plastic cell architecture: towards reconfigurable computing for general-purpose

Abstract: We propose a new architectural reference based on programmable logic devices that we call Plastic Cell Architecture (PCA). PCA is a reference for implementing a mechanism of a fully autonomous reconfigurability, which is also introduced in this paper. This reconfigurability is a further step toward general-purpose reconfigurable computing, introducing variable- and programmable-grain parallelism to wired logic computing. The PGA architecture is a fusion of an SRAM-based FPGA and cellular automata, where the cellular automata are dedicated to support the run time activities of the circuits configured on the architecture. PCA computing follows the object-oriented paradigm, in that the circuits are regarded as objects. These objects can be described in a hardware description language that features the semantics of dynamic module instantiation. Following the discussions on our research direction, this paper mainly focuses on the mechanism of autonomous reconfigurability and the PCA architecture.

Reconfigurable manufacturing system having a production capacity method for designing same and method for changing its production capacity

Abstract: A reconfigurable manufacturing system (RMS) having an adjustable structure is designed based upon market demand and can be readily changed from a first desired production capacity to a second desired production capacity to manufacture a desired amount of products from a family of products The RMS includes a plurality of workstations with reconfigurable machines and computerized numerically controlled (CNC) machines, a control system including a plurality of reconfigurable controllers, as well as a reconfigurable material handling system The reconfigurable machines may be reconfigurable machine tools having reconfigurable hardware that enables conversion of the machines by, for example, relocating their spindle units The RMS production capacity is quickly adjusted to market fluctuations in product demand The RMS functionality is easily adapted to fabrication of new products of the same product family The RMS possesses certain key characteristics (ie, modularity, integrability, customization, convertability, and diagnosability) that are needed for rapid and cost-effective reconfiguration A methodology for the design of an RMS, and a complementary methodology for changing the production capacity including reconfiguration and ramp-up of the RMS are also provided

Real-time 2-D feature detection on a reconfigurable computer

Abstract: We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA's). We envision this device as the front-end of a system able to track image features in real-time control applications like autonomous vehicle navigation. The algorithm employed to select good features is inspired by Tomasi and Kanade's method. Compared to the original method, the algorithm that we have devised does not require any floating point or transcendental operations, and can be implemented either in hardware or in software. Moreover, it maps efficiently into a highly pipelined architecture, well suited to implementation in FPGA technology. We have implemented the algorithm on a low-cost reconfigurable computer and have observed reliable operation on an image stream generated by a standard NTSC video camera at 30 Hz.

Improving functional density using run-time circuit reconfiguration [FPGAs]

Abstract: The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach.

Pebble: A Language for Parametrised and Reconfigurable Hardware Design

Abstract: Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be customised by different parameter values, such as design size and the number of pipeline stages. Such descriptions can be compiled without flattening into various VHDL dialects. Pebble improves design effectiveness by supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; it also supports run-time reconfigurable design. We introduce Pebble and the associated tools, and illustrate their application to VHDL library development and reconfigurable designs for Field Programmable Gate Arrays (FPGAs).

Automating production of run-time reconfigurable designs

Abstract: This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit configurations are matched to locate the components common to them, so that reconfiguration time can be minimized. The circuit configurations are represented as a weighted bipartite graph, to which an efficient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is device-independent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach.

Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine

Abstract: Most modern security protocols and security applications are defined to be algorithm independent, that is, they allow a choice from a set of cryptographic algorithms for the same function. Although an algorithm switch is rather difficult with traditional hardware, i.e., ASIC, implementations, Field Programmable Gate Arrays (FPGAs) offer a promising solution. Similarly, an ASIC-based key search machine is in general only applicable to one specific encryption algorithm. However, a key-search machine based on FPGAs can also be algorithm independent and thus be applicable to a wide variety of ciphers. We researched the feasibility of a universal key-search machine using the Data Encryption Standard (DES) as an example algorithm. We designed, implemented and compared various architecture options of DES with strong emphasis on high-speed performance. Techniques like pipelining and loop unrolling were used and their Effectiveness for DES on FPGAs investigated. The most interesting result is that we could achieve encryption rates beyond 400 Mbit/s using a standard Xilinx FPGA. This result is by a factor of about 30 faster than software implementations while we are still maintaining flexibility. A DES cracker chip based on this design could search 6.29 million keys per second.

A reconfigurable logic machine for fast event-driven simulation

Abstract: As the density of VLSI circuits increases, software techniques cannot effectively simulate designs through the millions of simulation cycles needed for verification. Emulation can supply the necessary capacity and performance, but emulation is limited to designs that are structural or can be synthesized. This paper discusses a new system architecture that dramatically accelerates event-driven behavioral simulation and describes how it is merged with emulation.

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

Abstract: The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

Abstract: Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-rate scheduling algorithm to deal with this problem. To the best of our knowledge, dynamically reconfigured FPGAs have not previously been used in hardware-software co-synthesis of embedded systems. Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.

On-line fault detection for bus-based field programmable gate arrays

Abstract: We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.