Showing papers on "Relaxation oscillator published in 2021"

A 0.35-V 5,200-μm 2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator

Abstract: This article describes a 2.1-MHz relaxation oscillator (RxO) for energy-harvesting Internet-of-Things (IoT) sensor nodes. The RxO features an asymmetric swing-boosted RC network and a dual-path comparator to surmount the challenges of sub-0.5-V operation while achieving temperature resilience. The former enables alternating the common-mode voltages at the output of the RC network to facilitate the sub-0.5-V operation, while the latter is outfitted with a delay generator for tracking the temperature-sensitive delay of the comparator. Prototyped in 28-nm CMOS, the RxO occupies a tiny footprint of 5,200 $\mu \text {m}^{2}$ . The power consumption is 1.4 $\mu \text{W}$ at 0.35 V. The measured temperature stability is 158 ppm/°C (average of seven chips) over −20 °C–120 °C. It scores the best energy efficiency (667 fJ/cycle) among the reported MHz-range RxOs and has a figure-of-merit (181 dB) that compares favorably with the state-of-the-art.

A fully/electronically controllable voltage-mode Schmitt trigger based on only single VDGA and its applications

Abstract: This article is objected to present a new fully/electronically controllable voltage-mode Schmitt trigger based on a modified voltage differencing gain amplifier (VDGA). It can offer both counterclockwise (CCW) and clockwise (CW) functions, without changing circuit topology. The proposed Schmitt trigger comprises merely one VDGA and three resistors. The hysteresis and amplitude of the output voltage of proposed Schmitt trigger can be independently controlled by corresponding bias currents of the VDGA. The modified VDGA was designed by a fully balanced differential transconductance technique based on 0.35 µm CMOS transistor technology, providing advantages in high gain, wide range of adjustability and symmetrical output signals. The performances of proposed Schmitt trigger were deeply investigated by not only simulation via PSpice program, but also experimental setup using commercially available integrated circuits. Both results agree well with the theoretical anticipation and are consistent each other. The total power consumption is approximately 1.39 mW at ± 1.5 V power supply. Additionally, to prove the practical use-abilities of the proposed Schmitt trigger, its applications in a voltage-mode relaxation oscillator, a triangular/square wave generator and a pulse width modulator are also included.

Analysis and Design of the Three-Inverter Schmitt Trigger for Supply Voltages Down to 50 mV

Abstract: This brief analyzes the operation of the three-inverter Schmitt trigger (TI-ST) at ultra-low supply voltages. Included in the analysis is a model to predict the supply voltage at which the TI-ST changes from the amplifier mode to the hysteresis mode. We show theoretically that the TI-ST can exhibit hysteresis for a supply voltage as low as the fundamental limit of unity gain of the CMOS inverter. We also demonstrate experimentally that, with a suitable design, hysteresis starts to occur from a supply voltage as low as 48.5 mV. A relaxation oscillator built with a TI-ST and standard inverters is experimentally demonstrated to start to oscillate from supply voltages as low as 62 mV.

High Resolution Frequency Measurement Techniques for Relaxation Oscillator Based Capacitive Sensors

Abstract: This work presents high resolution and adaptable frequency measurement techniques for relaxation oscillator based capacitive sensors. The techniques rely on extremely simple hardware such as a 1-bit coarse voltage quantizer to generate a 1-bit data stream and subsequently determine frequencies with resolutions greater than 20 bits from the 1-bit data stream. The proposed readouts are based on two types of 1-bit hardware approaches with Nyquist sampling in one approach and oversampling in the other. The first approach employs a Nyquist rate sampled 1-bit comparator while the second approach relies on an oversampled 1-bit quantizer based delta-sigma modulator (DSM) as a hardware to generate the bit stream. High resolution frequency is estimated from the 1-bit data stream using parametric, non-parametric and compressed sensing approaches. We provide detailed study and measurement results comparing the performance of the proposed techniques for test inputs with different frequencies and amplitudes and multiple signal shapes including sine, square, triangular and sawtooth. We show that the 1-bit comparator along with the CS approach provides the best performance across all input amplitude, frequency and shapes. A capacitive water level sensor was implemented in a PCB and embedded in a conventional square wave relaxation oscillator to verify the proposed technique. Measurement results show that incremental SNRs can be achieved only by increasing the 1-bit data stream length without any change in the hardware thereby demonstrating the adaptability of the technique based on an application requirement.

Using noise to augment synchronization among oscillators.

Abstract: Noise is expected to play an important role in the dynamics of analog systems such as coupled oscillators which have recently been explored as a hardware platform for application in computing. In this work, we experimentally investigate the effect of noise on the synchronization of relaxation oscillators and their computational properties. Specifically, in contrast to its typically expected adverse effect, we first demonstrate that a common white noise input induces frequency locking among uncoupled oscillators. Experiments show that the minimum noise voltage required to induce frequency locking increases linearly with the amplitude of the oscillator output whereas it decreases with increasing number of oscillators. Further, our work reveals that in a coupled system of oscillators-relevant to solving computational problems such as graph coloring, the injection of white noise helps reduce the minimum required capacitive coupling strength. With the injection of noise, the coupled system demonstrates frequency locking along with the desired phase-based computational properties at 5 × lower coupling strength than that required when no external noise is introduced. Consequently, this can reduce the footprint of the coupling element and the corresponding area-intensive coupling architecture. Our work shows that noise can be utilized as an effective knob to optimize the implementation of coupled oscillator-based computing platforms.

Post-Manufacturing Process and Temperature Calibration of a 2-MHz On-Chip Relaxation Oscillator

Abstract: In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about $I_{DD}=97.8\,\,\mu \text{A}$ at the nominal temperature of 42.5°C and nominal supply voltage of $V_{DD}=1.8$ V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V.

Creating Electronic Oscillator-based Ising Machines without External Injection Locking

Abstract: Coupled electronic oscillators have recently been explored as a compact, integrated circuit- and room temperature operation- compatible hardware platform to design Ising machines. However, such implementations presently require the injection of an externally generated second-harmonic signal to impose the phase bipartition among the oscillators. In this work, we experimentally demonstrate a new electronic autaptic oscillator (EAO) that uses engineered feedback to eliminate the need for the generation and injection of the external second harmonic signal to minimize the Ising Hamiltonian. The feedback in the EAO is engineered to effectively generate the second harmonic signal internally. Using this oscillator design, we show experimentally, that a system of capacitively coupled EAOs exhibits the desired bipartition in the oscillator phases, and subsequently, demonstrate its application in solving the computationally hard Maximum Cut (MaxCut) problem. Our work not only establishes a new oscillator design aligned to the needs of the oscillator Ising machine but also advances the efforts to creating application specific analog computing platforms.

A 300 nW 10 kHz Relaxation Oscillator with 105 ppm/ $$^{\circ }$$ ∘ C Temperature Coefficient

Abstract: An on-chip nanopower RC relaxation oscillator is developed in a 180-nm standard CMOS process, consuming 300 nW while running at 10 kHz. Employing a frequency compensation scheme that reduces the frequency drift introduced by comparator offset and delay, the proposed oscillator achieves a significant low temperature coefficient. Furthermore, a supply regulation structure is used to reduce the frequency sensitivity to supply voltage variations. Post-simulation results show that the frequency variation against temperature is 105 ppm/ $$^{\circ }$$ C in the temperature range from 0 to 85 $$^{\circ }$$ C, and the line sensitivity is 2.19%/V with the supply voltage changing from 1.05 to 1.45 V. At offset frequencies of 100 Hz and 1 kHz, the simulated phase noises are −50 and −71 dBc/Hz, respectively.

A Fully-Integrated Reference-Free Relaxation Oscillator with No Comparators

Abstract: A fully-integrated relaxation oscillator with a typical frequency of 1.37 MHz is proposed. Neither comparators nor the reference voltage is required in the proposed oscillator. A constant with temperature (CWT) current source has been utilized to achieve good temperature stability. Moreover, a conventional comparator has been replaced with a voltage controlled delay element (VCDE) to avoid the comparator offset effect. Fur­thermore, frequency variation against supply voltage has been eliminated by matching bias voltages of the current starved delay element (CSDE) in the ramp generator and VCDE. The proposed relaxation oscillator is implemented with 0.25 μm BCD process. The measured results show that the frequency variation against supply voltage is within ±0.6%.

A CMOS Integrated Low-Power, Ultra-Low-Frequency Relaxation Oscillator for Neuromorphic Applications

Abstract: In the emulation of dynamic activities of neurons, relaxation oscillator plays a decisive role in the form of frequency coding and frequency synchronization. This paper presents a programmable ultra-low-frequency relaxation oscillator for neuromorphic network applications. The oscillator adopts a 250 pA charging current to achieve ultra-low oscillation frequency and utilizes a subthreshold-region current mirror to realize negative differential resistance. The frequency of the proposed oscillator is configurable from 3.15 Hz to 81.30 Hz. The power consumption of a single oscillator is 24 nW with an area occupation of 0.05546 mm2. The design is fabricated in 130 nm CMOS technology with 3.3 V supply voltage. The functionality of the proposed design is proven with measurements.

Open Defect Detection in Assembled Circuit Boards With Built-In Relaxation Oscillators

Abstract: In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a built-in test circuit. The methods we followed are based on the oscillation frequency of a relaxation oscillator (ROsc) embedded in integrated circuits (ICs). The frequency is measured as the number of pulse signals within a specified test time. Using the test methods, open defects at the interconnects between IC pins and a printed circuit board (PCB) are detected that are modeled as a resistor, a capacitor, and an open-circuit fault. We examined the detectability of open defects using the process variations afforded by SPICE simulation. The simulation results show that open defects were detected, modeled as a resistor of 45.8 $\Omega $ or above, along with open defects modeled as a capacitor and an open-circuit fault using the production test method. In addition, a resistance increase of 1.2 $\Omega $ at defect-free interconnects occurred after shipping to market was detected using the field test method. We also prototyped ICs with embedded ROscs and built an experimental circuit made of the ICs on PCBs. Moreover, we experimentally examined whether open defects could be detected. The results show that with the production test method, open defects modeled as a resistor of 10 $\Omega $ or above and modeled as a capacitor and an open-circuit fault can be detected.

Control of Resonant Switched-Capacitor Converters

Abstract: A dynamic model for the nonlinear mixed-signal control loop of switch conductance regulation (SwCR) is proposed. The model allows to analyze the stability for this class of ReSC converters and, accordingly, to optimize the design of the control loop. An analytic stability criterion is derived based on a harmonic balance approach (also called describing function analysis) together with the dual locus method. The model is verified by measurements of the proposed resonant SC converter that operates up to a resonance frequency of 47 MHz. The presented modeling methodology can be applied to other areas, such as digital LDO, slope shaping, or digitally assisted analog.

Adaptive self-threshold strategy of high speed comparator-based relaxation oscillator using 0.18-μm low-power CMOS design

Abstract: This paper develops an integrated concept of a relaxation oscillator to increase system frequency stability and to provide anti-noise signals at a nominal frequency of 8.2 MHz using 2 swing-boosting and self-threshold tracking loop methods. In this case, based on the design of a low-power, high-speed CMOS, the proposed relaxation oscillator is provided, which develops high-speed at low power under various operating conditions. To reduce the dependence of the output voltage on the system temperature, considering self-threshold-tracking loop technique, the transient voltage signals from inverter-based comparator devices, the transient voltage signals from inverter-based comparator devices are matched to the corresponding nominal value of the reference voltage, taking into account the self-threshold tracking loop technique. In this way, the proposed self-threshold tracking loop technique compensates for the existing time delay that ensures the required power consumption of the power comparator. The proposed scheme procedure is provided for the design of the methodology considering a 0.18 μm CMOS. Regarding the design processes, an Allan noise variation of 1.56 ppm with − 109 dBc/Hz phase-based noises with an offset frequency of 100 kHz is provided, which develops a jitter period of 7.66 psrms period through the design process. In this case, the corresponding evaluations yield 160.8 dBc/Hz with 5.6 kHz/nW power comparison efficiency, using only 46.3 μW as power consumption. In this respect, the proposed compensation scheme provides a sensitivity of 0.9%/0.1 V, which is very low compared to other conventional loops. According to the proposed relaxation oscillator scheme, there is an internal temperature of 123 ppm/°C, which is evaluated by − 20–100 °C without considering a modification procedure.

Tuning method for current mode relaxation oscillator

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Low-Power High Sensitive Capacitance Read-Out Circuit Using a-InGaZnO TFTs

Abstract: This paper presents a capacitance readout circuit with high sensitivity and low power consumption using amorphous-Indium-Gallium-Zinc-Oxide thin-film transistors (a- InGaZnO TFTs). A relaxation oscillator is proposed to convert the sensor output (capacitance) into frequency. The proposed circuit has bootstrapping load to improve the output voltage swing using unipolar transistors. A differential to single ended converter and a buffer are used to get rail to rail output voltage. Simulation results show an improvement in sensitivity (832 Hz/pF) and power consumption (1.4 mW) as compared to the conventional ring oscillator based designs (142 Hz/pF, 1.9 mW) when circuits are simulated with a power supply of 10V, without compromising voltage swing. Therefore, this circuit finds potential application to implement sensing systems with flexible electronics.

Self-Referenced 32-kHz Rotating Capacitor Relaxation Oscillator with Chopped Comparator Offset-Voltage Cancellation

Abstract: This work presents a novel relaxation oscillator architecture using a rotating capacitor integrator and a chopped comparator. The oscillator is self-referenced, using the resistor instead of the current source, together with the reference voltage realized with the resistor divider connected to the supply voltage. The oscillator prototype is designed and manufactured in 180 nm technology, typically consumes 1.5 µA at 32 kHz, has a frequency variation of ±0.44% in the temperature range from −40 to 105°C and ±0.3% in the power supply range from 1.62 to 1.98 V. The oscillator has a start-up time of 15.4 µs and is operational in the low supply voltage range.

Low Power CMOS Thyristor-Based Relaxation Oscillator with Efficient Current Compensation

Abstract: This paper presents a microwatt voltage-mode relaxation oscillator, whose main innovation is the utilization of CMOS thyristor circuits as decision elements. It provides stable on-chip 140 kHz clock source for ultra-low power autonomous systems. The employment of CMOS thyristors reduces the dynamic power consumption compared to the classical topology, but introduces strong PTAT temperature dependency. This is compensated by a CTAT current reference, which recycles parts of the PTAT bias generation block and therefore relaxes overall chip area and power penalty. The reference start-up time is effectively decreased by a modified start-up circuit, which shortens system power-on. The oscillator excluding the recycled PTAT occupies 0.09 mm2 and draws 907.4 nW from 1.8 V supply, resulting in a Figure-of-Merit of 6.5 nW/kHz. With the PTAT reference accounted, 1.20 µW, 8.6 nW/kHz and 0.11 mm2 were achieved. Measurements show a temperature coefficient of −514.7 ppm/K in the range of −40°C to 85°C with the proposed compensation, achieving an improvement of 5.5 times compared to the simulated uncompensated case. The frequency variation is 2.62 %/V N within supply voltage range of 1.5 V to 2.5 V.

Relaxation Oscillator Using Closed-loop Dual Comparator for Biomedical Applications

Abstract: People's rising concerns about health have fueled research into high-performance biomedical devices and circuits, such as sensors and implantable systems on a chip. It is important for these biomedical devices to operate at the same low frequency to treat certain organs and diseases. Thus, the clock generator needs to be able to provide low frequency clock pulses with minimal size and high reliability. These constraints elevate power consumption and production cost within the circuit design to key parameters. One promising candidate is relaxation oscillator which has good on-chip compatibility, and superior frequency stability. This paper proposes a novel relaxation oscillator using closed-loop dual comparator. A frequency in the band of 50Hz to 2.5kHz can be generated by replacing the value of resistors and capacitor in all possible combinations. The simulation and experimental result confirm that closed-loop dual comparator-based relaxation oscillator provides low frequency with lower cost and more simplicity due to fewer components.

Analysis and Design of Continuous-Time Comparator

Abstract: Applications of continuous-time (CT) comparator include relaxation oscillators, pulse width modulators, and so on. CT comparator receives a differential input and outputs a strobe ideally when the differential input crosses zero. Unlike the DT comparators with positive feedback circuit, amplifiers consuming static power must be employed in CT comparators to amplify the input signal. Therefore, minimization of comparator delay under the constraint of power consumption often becomes an issue. This paper analyzes transient behavior of a CT comparator. Using “constant delay approximation”, the comparator delay is derived as a function of input slew rate, number of stages of the preamplifier, and device parameters in each block. This paper also discusses optimum design of the CT comparator. The condition for minimum comparator delay is derived with keeping power consumption constant. The results include that the optimum DC gain of the preamplifier is e∼e3 per stage depending on the element which dominates load capacitance of the preamplifier. key words: comparator, continuous time, analysis, optimization, relaxation oscillator, pulse width modulator, single-slope A/D converter

Relaxation oscillator and method

Abstract: A relaxation oscillator and a method of controlling the relaxation oscillator are disclosed. The relaxation oscillator includes a reference voltage generating circuit configured to generate a reference voltage based on a transistor-based resistor, a variable voltage generating circuit configured to generate a variable voltage based on the reference voltage and a control switch, a threshold voltage generating circuit configured to generate a threshold voltage using a switched-capacitor resistor circuit, and a switch control circuit configured to output a control signal to control the control switch based on the variable voltage and the threshold voltage.

Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation Oscillator

Abstract: This paper presents a relative slope-boosting technique for a capacitive sensor circuit based on a relaxation oscillator. Our technique improves jitter, i.e. resolution, by changing both the voltage slope on the sensing and the reference sides with respect to the sensor capacitance. The sensor prototype circuit is implemented in a 180-nm standard CMOS process and achieves resolution of 710 aF while consuming 12.7 pJ energy every cycle of 13.78 kHz output frequency. The measured power consumption from a 1.2 V DC supply is 430 nW.

Crystal oscillator circuit based on multiphase injection oscillator

Abstract: A crystal oscillator circuit based on a multiphase injection oscillator adopts a novel relaxation oscillator with multi-phase excitation signal output, utilizes a switch matrix to uniformly switch thesignals, outputs the signals to a crystal for energy injection, enables the crystal to start oscillation quickly in a short time, and on the premise of ensuring low power consumption, tstarting timeis close to the minimum theoretical value, the steady-state output swing amplitude is large, and the problem that the injection frequency of a traditional injection technology is not accurate is solved.

Relaxation oscillator having a dynamically controllable current source

Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

A 5.02nW 32-kHz Self-Reference Power Gating XO With Fast Startup Time Assisted by Negative Resistance and Initial Noise Boosters

Abstract: We present a 32.768 kHz crystal oscillator with ultra-low power operation and a fast startup featuring for IoT applications. A self-reference power gating scheme detects the amplitude of a clock, enabling a negative resistance booster to awake XO and keep the oscillation with a duty-cycling technique for minimizing power consumption. In addition, a relaxation oscillator injects in-band noise initially, further reducing the startup time. The prototype XO for proof-of-concept was fabricated in 0.11- $\mu \text{m}$ CMOS and fully characterized. It consumes 5.02 nW at 0.5-V supply and achieves the startup time of 1.26 s simultaneously.

Linearizing Relaxation-Oscillator Based Front-End for Magneto-Resistive Angle Sensors

Abstract: This paper presents a new linearizing digital front-end for magneto-resistive (MR) angle sensor having sine and/or cosine transfer-characteristics. The front-end processes a dual half-bridge MR sensor and then outputs a linear indication of the sensing angle. It combines a simple relaxation-oscillator-based circuit with linearizing ratiometric technique to achieve the aforementioned task. The front-end provides several positive features such as (1) no requirement of precision and matched bipolar reference voltages, (2) simplicity of architecture, (3) independence from various circuit non-idealities. A detailed account of the proposed front-end is discussed with the help of systematic mathematical derivation. The performance of the front-end is verified with help of simulation as well as experimental studies and reported in this paper.

Low power electronic oscillators

Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator (2) having an active state and an inactive state; a bias current circuit portion (16) arranged to provide a bias current (14) to the relaxation oscillator (2) during said active state; and an electronic switch (12) arranged to isolate said relaxation oscillator (2) from the bias current circuit portion (16) when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current (14) and the bias current circuit portion (16) is arranged to use the stored internal voltage value to generate the bias current (14) when the oscillator (2) is started up from the inactive state to the active state.