Topic
Relaxation oscillator
About: Relaxation oscillator is a research topic. Over the lifetime, 1952 publications have been published within this topic receiving 22326 citations.
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TL;DR: In this paper, the decay of the nuclear magnetization when it precesses in a plane perpendicular to the constant magnetic field is observed and a method for measuring transverse relaxation times in liquids is described.
Abstract: A method for measuring transverse relaxation times in liquids is described. The method is based on the observation of the decay of the nuclear magnetization when it precesses in a plane perpendicular to the constant magnetic field. This condition is realized by stopping the variation of the constant magnetic field during a fast adiabatic passage at a proper time. The constant magnetic field is modulated with a sawtooth current from a relaxation oscillator and an amplifier. When the voltage induced by the nuclear precession reaches a fixed value the relaxation oscillator is stopped with a delay such that the constant field stops its variation at the value for which the signal has the largest amplitude. Measurements have been made on some pure liquids and the preliminary results indicate that the values ofT
2 are very close to those ofT
1.
9 citations
TL;DR: A novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy and the power consumption was only 0.457 mW.
Abstract: This paper presents a novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy. It consists of a relaxation oscillator comprising a hysteresis Schmitt trigger and a timing integrator, along with frequency divider (FD) stages and path selector output for driving an electrode from 16 selectable channels. It was fabricated using Global Foundries 8RF-DM 130-nm CMOS process with a supply voltage of ±1 V for the oscillator and +1 V for logic circuits. The WFG provides an output of around 1.5 $\text{V}_{\textrm {p-p}}$ at a nominal low oscillation frequency of 17 kHz using small-size on-chip passive components of values 10 $\text{k}\Omega $ and 10 pF. The WFG core (band I) can be tuned in the range 6.44–1003 kHz through bias current adjustment, while a lower frequency (band II) in the range 0.1 Hz–502 kHz can be provided digitally through a $\div 2$ stage. The power consumption was only 0.457 mW for the WFG and 2.1 mW for the FD circuit while occupying a total silicon area of only 18 $426~\mu \text{m}^{2}$ .
9 citations
01 May 2017
TL;DR: Simulated results demonstrated that the proposed ROSC generates 32.5-kHz clock frequency and achieves ultra-low power dissipation of 271 nW and Monte Carlo statistical simulations showed that the mean, standard deviation, and the coefficient of variation are 32.3 kHz, 0.6 kHz, and 1.9%, respectively.
Abstract: In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low power real-time clock (RTC) applications. The proposed ROSC is based on a conventional ROSC and modified to be area-efficient circuit configuration, without using resistors. The proposed ROSC consists of a bias current source, proportional to absolute temperature (PTAT) voltage source, current mode ROSC, shunt regulator, and output logic circuit. The PTAT voltage source and shut regulator are used to compensate for the temperature characteristics of the ROSC. By implementing our proposed ROSC in a 65-nm CMOS process, the area was 0.022 mm2. Simulated results demonstrated that our proposed ROSC generates 32.5-kHz clock frequency and achieves ultra-low power dissipation of 271 nW. The temperature and voltage dependences of the oscillation frequency were 138ppm/°C and 13.9ppm/mV, respectively. Monte Carlo statistical simulations showed that the mean, standard deviation, and the coefficient of variation are 32.3 kHz, 0.6 kHz, and 1.9%, respectively.
9 citations
TL;DR: A dynamic common-gate comparator is proposed to reduced the power, combined with a slope boosting technique to reduce the period jitter, and a peak-detecting feedback loop is implemented to maintain frequency stability over temperature variations.
Abstract: This brief presents a low-power low-jitter relaxation oscillator for on-chip low-frequency clock generation. A dynamic common-gate comparator is proposed to reduce the power, combined with a slope boosting technique to reduce the period jitter. A peak-detecting feedback loop is implemented to maintain frequency stability over temperature variations. The oscillator achieves 0.025% period jitter and 70 ppm/°C temperature coefficient while consuming 1.36 $\mu \text{W}$ at 364 kHz with a 1.2-V supply.
9 citations
Patent•
09 Aug 1973TL;DR: In this article, a dead-zone comparator is defined as a set-reset buss to the memory element, which is used to compare an input signal to a high reference level and to a low reference level, which reference levels can be programmed.
Abstract: A dead-zone comparator includes first and second voltage comparators used respectively to compare an input signal to a high reference level and to a low reference level, which reference levels can be programmed. A bistable memory element is set by the output signal of one comparator and reset by the output signal of the other. These SET and RESET signals are opposite polarity currents, one of which is more severely constrained in value than the other, and are applied via a common SET-RESET buss to the memory element. When the memory element is in its SET condition, a relaxation oscillator is permitted to deliver output pulses of sufficient magnitude to trigger SCR''s or triacs directly. When the memory element is in its RESET condition, the relaxation oscillator is prevented from furnishing any output pulses.
9 citations