Relaxation oscillator

About: Relaxation oscillator is a research topic. Over the lifetime, 1952 publications have been published within this topic receiving 22326 citations.

Fll oscillator/clock with an fll control loop including a switched capacitor resistive divider

Abstract: In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider (130) that converts fosc to a resistance, generating an FLL feedback voltage (Vfosc) to generate a loop control signal (OSC cntrl) input to the oscillator (110). In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock generator (100) operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

Integrated circuit equipped with programmable internal clock

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit equipped with an internal clock having no such defect that an oscillating frequency fluctuates in dependence on a power supply voltage of a circuit or variation in manufacturing. SOLUTION: In this integrated circuit, a processor (CPU) and an oscillator (OSC) are integrated in the same substrate, and a data resistor (R1) which can be loaded by the processor is provided. The oscillator functions as a clock for the processor, and is a relaxation oscillator equipped with a capacitor (C) and a current source for charge and discharge of the capacitor. The data resistor controls frequency adjustment of the relaxation oscillator by controlling the value of the charge and discharge current of the capacitor, and is loaded by the processor from an electrically programmable and nonvolatile memory (M1) provided in the same substrate of the integrated circuit while storing frequency correction data.

Low power low voltage quadrature RC oscillators for modern RF receivers

Abstract: Faculdade de Ciencias e Tecnologia Departamento de Engenharia Electrotecnica e de Computadores Mestre em Engenharia Electrotecnica e de Computadores by Hugo Filipe da Rocha Lopes This thesis proposes a study of three di erent RC oscillators, two relaxation and a ring oscillator All the circuits are implemented using UMC 130 nm CMOS technology with a supply voltage of 12 V We present a wideband MOS current/voltage controlled quadrature oscillator constituted by two multivibrators Two di erent forms of coupling named, soft (traditional) and hard (proposed) are di erentiated and investigated It is found that hard coupling reduces the quadrature error and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling The behaviour of the singular and coupled multivibrators is investigated, when an external synchronizing harmonic is applied We introduce a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic ltering and resistor feedback, to reduce phase-noise The designed circuit has a very low phase-noise, -1326 dBc/Hz @ 10 MHz o set, and the power consumption is only 1 mW, which leads to a gure of merit (FOM) of -1591 dBc/Hz The nal circuit is a two integrator fully implemented in CMOS technology, with low power consumption The respective layout is made and occupies a total area of 5856x10−3 mm, post-layout simulation is also done UNIVERSIDADE NOVA DE LISBOA

Non-ideal behavior of a comparator-based relaxation oscillator

Abstract: The non-ideal behaviour of a classical comparator-based first-order relaxation oscillator is analysed. The influences of the comparator slew-rate and output resistance as well as the parasitic resistances of the reactive element are considered. Numerical simulations at system level and transistor level are given.

Quadrature generation techniques in CMOS relaxation oscillators

Abstract: Shunt and series-coupling techniques for quadrature generation are applied to CMOS relaxation oscillators. The 2.4GHz quadrature oscillators are designed and simulated in a UMC 0.18µm CMOS process. The shunt-coupled oscillator consumes a current of 12mA from a supply of 1.8V and achieves a phase noise of −99.4dBc/Hz @ 1MHz offset. The series-coupled oscillator consumes a current of 16mA from the 1.8V supply and achieves a phase noise of −98.3dBc/Hz @ 1MHz offset. For a systematic mismatch of 1%, the quadrature phase error of the shunt-coupled and series-coupled circuits are 0.55° and 0.1° respectively.