Relaxation oscillator

About: Relaxation oscillator is a research topic. Over the lifetime, 1952 publications have been published within this topic receiving 22326 citations.

Voltage to frequency converter for DAC test

Abstract: In this paper a modified relaxation oscillator is proposed as the core of an analog to digital modulator for on chip signal extraction for test. The architecture uses digital current source generation and digital switching in place of active circuitry. The resulting design allows for high input sensitivity, robustness to component variation while occupying little silicon area. This paper provides solutions on the main challenges in implementing this modulator and how it may be integrated with a digital based tester.

Collective phenomena in large populations of globally coupled relaxation oscillators

Abstract: We present a study of a large pool of globally coupled relaxation oscillators. The reaction of the pool to the presence of a modulating external field is discussed. The coupling is assumed homogeneous and linear. Randomly distributed internal frequencies introduce a disordering element that, due to the coupling, can result in oscillator quiescence. Self-synchronization is shown to be absent in this system. However, this is entirely due to the linear coupling. For identical oscillators the basic state is incoherent and marginally stable in an extended region of parameter space. With modulation on the levels, the average rotation number as function of the external frequency lies on a devil's staircase, as for a single oscillator. However, the locked regions shrink with increasing coupling

Low power oscillator with negative resistance boosting

Abstract: Representative implementations of devices and techniques provide increased negative resistance to an oscillator circuit. A capacitance divider and/or a feedback loop may be employed to increase the negative resistance of the oscillator circuit at the same current consumption and with the same load capacitance. Further, a constant bias circuit may be employed to conserve and/or reduce the current consumption of the oscillator circuit.

A 0.016 mm 2 0.26- $\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Abstract: Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 $\mu \text{W}$ /MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator’s delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50–300 MHz output frequencies from a reference clock in the range of 0.5–5 MHz. The DPLL occupies an active area of 125 $\mu \text{m}\times125\mu \text{m}$ and achieves ±0.33% period jitter while consuming 63.5 $\mu \text{W}$ at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 $\mu \text{W}$ /MHz at 0.8-V supply voltage.