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Relaxation oscillator

About: Relaxation oscillator is a research topic. Over the lifetime, 1952 publications have been published within this topic receiving 22326 citations.


Papers
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Proceedings ArticleDOI
01 Nov 2015
TL;DR: In this article, the negative resistance theory of FET was used to design the dielectric resonator oscillator (DRO) operating frequency is 10.5GHz and the output impedance is - 50.15+j 0.604, meet the negative resistor circuit design, and output power is 7.95 dBm.
Abstract: In RF wireless communication systems, oscillator plays the role of providing signals, therefore high stability and low phase noise oscillator is very important. This paper use the negative resistance theory of FET, let the circuit is in an unstable state. And the use of dielectric resonator (DR) as a signal source, design of the dielectric resonator oscillator (DRO) operating frequency is 10.5GHz. Use dielectric resonator (DR) of stable frequency characteristics, high Q value characteristics, make the oscillator with a small, low phase noise and other advantages. The design process using the software Agilent's ADS for optimization and analysis results. Final, the output impedance is - 50.15+j0.604, meet the negative resistance circuit design, and output power is 7.95 dBm.
Journal ArticleDOI
TL;DR: In this paper, a relaxation oscillator is proposed to increase system frequency stability and to provide anti-noise signals at a nominal frequency of 8.2 MHz using 2 swing-boosting and self-threshold tracking loop methods.
Abstract: This paper develops an integrated concept of a relaxation oscillator to increase system frequency stability and to provide anti-noise signals at a nominal frequency of 8.2 MHz using 2 swing-boosting and self-threshold tracking loop methods. In this case, based on the design of a low-power, high-speed CMOS, the proposed relaxation oscillator is provided, which develops high-speed at low power under various operating conditions. To reduce the dependence of the output voltage on the system temperature, considering self-threshold-tracking loop technique, the transient voltage signals from inverter-based comparator devices, the transient voltage signals from inverter-based comparator devices are matched to the corresponding nominal value of the reference voltage, taking into account the self-threshold tracking loop technique. In this way, the proposed self-threshold tracking loop technique compensates for the existing time delay that ensures the required power consumption of the power comparator. The proposed scheme procedure is provided for the design of the methodology considering a 0.18 μm CMOS. Regarding the design processes, an Allan noise variation of 1.56 ppm with − 109 dBc/Hz phase-based noises with an offset frequency of 100 kHz is provided, which develops a jitter period of 7.66 psrms period through the design process. In this case, the corresponding evaluations yield 160.8 dBc/Hz with 5.6 kHz/nW power comparison efficiency, using only 46.3 μW as power consumption. In this respect, the proposed compensation scheme provides a sensitivity of 0.9%/0.1 V, which is very low compared to other conventional loops. According to the proposed relaxation oscillator scheme, there is an internal temperature of 123 ppm/°C, which is evaluated by − 20–100 °C without considering a modification procedure.
Proceedings ArticleDOI
01 Dec 2017
TL;DR: The study conducted, to evaluate the effect of coupled interference from a distribution power line, showed that the sensitivity of the output to the interference is negligible for a large range and a method is proposed to further increase this range and to improve the resolution of the proposed conversion method.
Abstract: A new interference-insensitive Switched Capacitor (SC) Capacitance-to-Digital Converter (CDC) is presented in this paper. The insensitivity is achieved by the conversion mechanism itself. It is a combination of a SC relaxation oscillator and an integrating type analog-to-digital converter whose integration time is made an integer multiple of the time period, T intr , of the interfering signal. Although in a typical dual-slope converter, the integration time can be set as a suitable multiple of T intr , the deintegration time is a function of the measurand. Thus, the extent of interference rejection that can be achieved, using such converters, is limited. The SC relaxation oscillator in the proposed CDC is operated for a fixed duration to make a measurement. This duration is set as a multiple of the T intr . In this scheme, the final output is proportional to the number of transitions in the output of the SC relaxation oscillator which is directly proportional to the value of the sensor capacitance and has negligible sensitivity to the presence of the interference signal. The proposed scheme has been realized and tested using a SPICE tool. The non-linearity of the scheme is found to be less than 0.1% for a sensor capacitance, varied from 15 pF to 25 pF. The study conducted, to evaluate the effect of coupled interference from a distribution power line, showed that the sensitivity of the output to the interference is negligible for a large range. This paper also proposes a method to further increase this range and to improve the resolution of the proposed conversion method. The proposed converter is suitable for capacitive sensors that are used in the consumer applications.
Patent
21 Sep 2004
TL;DR: In this paper, a circuit and a method are given, to realize and implement an oscillator circuit with a Smart Current Controlled (SCC) Resonator Driver, which produces a controlled driving current for the resonator element during operation in both phases of the oscillation cycle to reach for low phase noise and reduced power consumption.
Abstract: A circuit and a method are given, to realize and implement an oscillator circuit with a Smart Current Controlled (SCC) Resonator Driver. A newly introduced controlled current source for a crystal oscillator's amplifier element produces a controlled driving current for the resonator element during operation in both phases of the oscillation cycle to reach for low phase noise and reduced power consumption of the circuit. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.
Patent
22 Jun 2021
TL;DR: In this paper, a relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit, which is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive nodes.
Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202322
202242
202128
202044
201962
201855