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Showing papers on "Residual frame published in 1981"


Patent
20 May 1981
TL;DR: In this paper, a modified fast frame recorder is presented, where information corresponding to the object of interest is sampled a plurality of times for each recorded frame to provide an increased frame rate (e.g., 12,000 frames per second).
Abstract: Fast frame recorder apparatus is known wherein information corresponding to an object of interest is recorded at a fast frame rate (e.g., 2,000 frames per second) and displayed at a slower frame rate (e.g., 60 frames per second) to produce a slow motion replay of the object. In accordance with the present disclosure, such apparatus is so modified that information corresponding to the object of interest is sampled a plurality of times for each recorded frame to provide an increased frame rate (e.g., 12,000 frames per second) with respect to the object of interest.

72 citations


Patent
25 Mar 1981
TL;DR: In this article, the difference between the picture element value of a digitalized input picture signal and the outputs of respective frame memories is subtracted by respective subtractors, and a difference comparator is used to compare the absolute values of outputs from the subtractors and changes over switching circuits 7, 8 to the subtractor whose absolute value is smaller.
Abstract: PURPOSE:To encode between frames always with high forecasting precision in two frame memories and to improve encoding efficiency by changing appropriately the output of one frame memory of which forecasting error value is smaller than that of the other. CONSTITUTION:A back picture is written in the 1st frame memory 2 and an input picture preceding by one frame is written in the 2nd frame memory 4. The difference between the picture element value 1 of a digitalized input picture signal and the outputs of respective frame memories 2, 4 are subtracted by respective subtractors 3, 5. A difference comparator 6 compares the absolute values of outputs from the subtractors 3, 5 and changes over switching circuits 7, 8 to the subtractor whose absolute value is smaller. The output of the switching circuit 7 is quantized and variable length encoded by a quantizing circuit 9 and a variable length encoder 11. A control signal indicating the status of the switching circuits 7, 8 is generated by a control signal generator 12 and the control signal and the output of the variable length encoder 11 are multiplexed by a multiplexer 13 and the multiplexed signal is sent through a buffer memory.

5 citations