Showing papers on "Residual frame published in 1985"

Synchronous data receiver circuit

Abstract: The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on.

Image correspondence techniques using serial neighborhood processing

Abstract: A serial neighborhood processing system, preferably employing a pipeline of individually programmable stages, is used to detect image correspondence between multiple frames of image data. Similar features in each frame are extracted utilizing a series of dilation and erosion sequences. In particular, landmarks in each frame are condensed to single image points having exactly one corresponding point in the other frame surrounding it within a given mathematical distance. The second frame of pixel data is registered with the first frame as a function of the spatial relationship between these pairs of matched points in the two reduced frames. A comparison is made between the first frame and the registered second frame to detect differences therebetween. Motion detection, stereo projection, registration of multidate Landsat imagery and matching images of electrophoretic gels are examples of particular uses for the techniques disclosed.

Image-sequence compression using a motion-compensation technique

Abstract: A motion-compensated image-sequence compression technique is disclosed in which the motion of an object point in a video screen occurring between the present frame and the following frame is predicted. The technique, useful in video teleconferencing, comprises calculating an initial estimate of the displacement of the object point and recursively updating the initial displacement estimate. The step of calculating an initial displacement comprises projecting the displacement forward along the trajectory of the motion of the object point from the present frame to the following frame.

Frame synchronization device

Abstract: Frame synchronization devices utilize a frame alignment word decoder connected to the outputs of a shift register which receives on its input the received data bit stream. It is clocked by a clock signal generated from a selection of periods of the data bit stream timing signal reproducing a periodic pattern. This pattern is formed by relative bit locations within the duration of a frame certain at least of which are distributed according to the distribution of the bits of an alignment word in a frame and which form groups of the same size regularly distributed over the duration of a frame. This clock signal is generated in the device by a divider which divides by 20 or by 21 which imposes on it a periodic phase skip by the value of one period of the data bit stream timing for as long as the alignment word is not recognized by the decoder. The shift register is implemented in two parallel parts clocked by versions of the clock signal with a relative phase shift between them, one of which parts updates the other part in parallel on each phase skip of the clock signal.

Recovery of frame alignment word having bits distributed in a digital transmission signal

Abstract: A frame alignment word has N predetermined bits distributed in the frame of a digital transmission signal. Each frame is divided into a number of sectors. Each sector has a heading made up of a bit or a bit group from the alignment word such that when placed end to end the headings in the frame form the alignment word. According to a frame alignment recovery method, bit groups are successively taken from the digital signal received at the sector frequency, each taken group having a maximum bit number equal to the bit number in each heading. The taken bit groups are compared with the heading bits corresponding in the frame alignment word and N-1 circular permutations thereof. The comparison are halted before reaching the full alignment word once the comparison of bits between the heading bits and taken successive groups reveals some disagreement.

Dual access frame store for field or frame playback in a video disk player

Abstract: A video player, specially adapted to accommodate "mixed field and frame" recordings, incorporates a frame store for playing back still pictures recorded on a magnetic disk as either single field or dual field (full frame) video signals A repetitive, interlaced output signal is taken from the frame store either directly or through an interpolation circuit While interpolation benefits single field playback, it is particularly useful for incrementally achieving full frame playback: An interpolated frame is provided for displaying a single field recording and for displaying a still picture before--and until--the second frame of a full frame recording is fully available from the frame store Once both fields of the picture are stored in the frame store, then and only then is the disk drive motor turned off, albeit that an interpolated frame is displayed before this occurs

Method and apparatus for multiplexing television signals

Abstract: A multiplexer for compressing two television programs into the bandwidth normally required for a single television signal is disclosed wherein vertically adjacent lines in the odd and even field of each frame are summed and differenced in pairs having the same color subcarrier phase. "Line pair signals" respectively comprising the sum and difference of each line pair are then formed after the difference signal is time compressed without an overall increase in bandwdth. The line pair signals for each frame of one program are alternately transmitted with the line pair signals of a frame from the second program. The line pair signals of a video frame are fewer in number and longer in duration than NTSC field lines. Timing is such that one frame of both programs is transmitted during the time allotted to the transmission of one frame under the NTSC standard. The lines from odd fields of each program are reconstructed after transmission by adding the appropriate difference signals and sum signals. The lines from even fields are reconstructed by differencing the sum signals and the difference signals.

Interflame prediction decoder

Abstract: PURPOSE: To display a picture without error by providing the second frame memory for storing the frame data ahead of the frame data stored in the first frame memory. CONSTITUTION: A frame memory 5 for storing the frame data ahead of the frame data stored in a frame memory 2 is provided. When an error is detected in an error detecting part 3', switches SW1, SW2 are controlled and as the data fed to a display device 4, the data stored in the frame memory 5 is transmitted. Thereby, the frame data stored in the frame memory 5 is the frame data preceding the generated error, so that is has no error and a picture having no error is displayed until the new data comes to the display device 4. COPYRIGHT: (C)1987,JPO&Japio

Image encoding and transmitting system

Abstract: PURPOSE: To improve transmission efficiency by thinning out every other one of image frames and executing reading from and writing in a transmission/ reception double buffer in an encoded image frame unit to form a data frame with header and by transmitting the said data. CONSTITUTION: From the data outputted from an A/D converter 1, one image frame out of every two is thinned out through an image encoding circuit 100, and is supplied to a transmission buffer 101. The buffer 101 comprises first and second buffers, and its input and output are alternately switched by the control from a controller 107. A header generating circuit 15 generates the header information of the transmital data frame. The said header information is multiplexed with the encoding data etc. by a transmital data multiplexing circuit 16. Thereafter, an error correction code is added to the said multiplexed data, and a frame synchronizing patter is inserted to constitute the transmital frame. COPYRIGHT: (C)1986,JPO&Japio

Coding system between frames and in frame

Abstract: PURPOSE: To prevent reduction in the coding efficiency by switching the coding means so as to apply in frame coding because the inter-frame correlation is small at scene change. CONSTITUTION: A coding means applying in frame coding and inter-frame coding and a discriminating section 15 comparing the in frame correlation between an input signal (a) and a signal retarding the input signal (a) for a prescribed picture element number by a delay circuit 12 and the inter-frame correlation between the input signal (a) and an inter-frame forecast (d) detected from a frame memory 9 and discriminating the quantity, are provided. When the discriminating section 15 discriminates that the in frame correlation is large, the coding is switched to the in frame coding and when it is discriminated that the inter- frame correlation is larger, the coding is switched into the inter-frame coding. COPYRIGHT: (C)1986,JPO&Japio

Real time single frame memory for converting video interlaced formats

Abstract: A circuit for converting interlaced video data to nonin­ terlaced video data at 30 frames per second, real time video rate, where rows of successive lines of video data applied to a single frame memory (4) are provided having data control means including write-in (7) and read-out (8) means for initi­ ally sequentially loading each row of memory with lines of interlaced video data of the first frame sequentially applied to the memory, and thereafter reading out successive mem­ ory rows of the first frame memory, while replacing each line read-out by whichever line of the second frame is applied to memory in real time just after read-out, until all lines of data of the second frame have been inserted into memory. Suc­ cessive frames are read out using a row addressing incre­ ment of N/2 for the next frame and repeating similar write-in and read-out of subsequent frames while multiplying the denominator of the address incrementing factor by two for each subsequent frame until the factor would be less than unity, and thereafter increasing the factor back to N/2 to re­ peat the cycle so as to process subsequent frames.

Error control coding system

Abstract: PURPOSE: To reproduce data at the receiving side and to execute the data communication with a high transmission efficiency at the transmission line to generate the burst characteristic error even when the receiving input level is low by selecting the frame length by an NAK signal or an ACK signal with a frame length selecting means CONSTITUTION: When an error is detected by a decoding device 106, a control information sending means 108 sends the frame number with an error to a coding device 109 together with an NAK signal, provides a cyclic code and an error correcting code, modulates by a modulator 110, sends to a communication channel 111, demodulates by a demodulator 112 and decodes by a decoder 113 Next, the error frame number is resent from a receiving side to a transmitting side together with the NAK signal, the NAK signal is decided by a frame length selecting part 1141 of a frame length selecting means 114 at the transmitting side, either of frame lengths L1∼L4 of a frame length memory device 1142 is selected by the condition, and the input data are sent to a coder 102 by the frame length Thus, the data are reproduced at the receiving side, the error of the burst characteristic is generated, and the data communication with a high transmission efficiency is executed COPYRIGHT: (C)1986,JPO&Japio

Encoder capable of removing interaction between adjacent frames

Abstract: In an encoder for encoding an input signal (AA) into a sequence of excitation pulses (GG) with reference to an autocorrelation signal (DD) and a cross-correlation signal (CC) derived from the input signal, a cross-correlation controller (40) controls the cross-correlation signal in response to the autocorrelation signal and the excitation pulse sequence by producing a control signal (HH). Both of the cross-correlation and the autocorrelation signals are concerned with a current frame of the input signal and a part of the following frame. The control signal appears in the following frame to be subtracted from the cross-correlation signal in a subtractor (31) and to modify the cross-correlation signal into an adjusted cross-correlation signal (EE). Although the adjusted cross- correlation signal lasts for the current frame and the part of the following frame, an excitation pulse generator (32) produces the excitation pulses only within the current frame.

Arrangement for the synchronisation of a digital data receiver

Abstract: Arrangement for the synchronisation of a digital data receiver to the bit clock and frame clock of a received data stream by correlation of a received frame alignment signal with a reference frame alignment signal stored in the data receiver. The correlation is performed in a digital correlator in time steps of 1/N bit lengths, N = an integer. When a frame alignment signal is detected, the correlator emits a setting pulse, from which the bit clock and frame clock are simultaneously derived.

Frame synchronizing system

Abstract: PURPOSE:To shorten the time of restoration of synchronism and to suppress increase of auxiliary data bits and continuity of information data ''0'' by inserting a complementary code of the preceding block frame pulse of a block including the frame pulse in the code form of a digital communication system. CONSTITUTION:It is noticed that a pulse -F2 is the complementary code of a frame pulse F2, and received data and data obtained by delaying received data through a one-bit delay circuit 3 by onebit are supplied to a comparing circuit 4. The comparing circuit 4 compares the input time of a frame synchronizing signal with the bit of received data and the bit one-bit delayed received data, and acquisition of synchronism is discriminated if these bits are F1 and -F1 or F2 and -F2 at the frame synchronizing signal input time, but otherwise, synchronism is not acquired. If synchronism is not acquired, a signal is sent to a frame synchronizing signal generating circuit 5, and the frame synchronizing signal generating circuit 5 uses a clock to shift the frame synchronizing signal by onebit, and comparison is performed again with this frame synchronizing signal by the comparing circuit 4. This operation is repeated until frame synchronism is acquired.

Method for splicing non-consecutive video signal frames

Abstract: A method for editing and splicing color videograms. A first video tape machine records videogram sequences contained on a video tape in a second machine. The sequence includes a first frame series terminated with a final frame and a second frame series which begins with a first frame. A discontinuity between the first and second frames is detected when the chrominance coding of the adjacent recorded frames is found to be the same instead of on an alternate basis. Each frame of the second frame series is shifted under these conditions in order that each video line subsequent to the first video line is shifted forward. The first video line is reduced to a black level. The method avoids the consequences of a splice between groups of frames when the frames on each side of the splice do not have the required opposite chrominance coating.

Method and device for error protection suitable for the digital transmission of data frames

Abstract: 1. An error protection method adapted to the transmission of framed digital data, wherein each frame comprises a number N1 of bits to be particularly protected and a number N2 of other bits, characterized in that it consists, on the transmission side, in encoding the N1 bits to be protected by an extinction correction encoding that introduces a redundancy R, the R.N1 bits resulting from this encoding on the one hand, and the N2 other bits on the other hand being distributed in constant proportions over a number B of data blocks forming a frame and being transmitted successively and independently from one another, and in that, on the reception side, a frame is declared valid when at most B(R-1)/R blocks are extinguished or false, the protected N1 bits of a valid frame being restituted via the extinction correction decoding, and the unprotected N2 /B bits of the extinguished or false blocks of a valid frame being replaced by a predetermined sequence of N2 /B bits.

Method for data reduction, especially data which are obtained during detection of optically detected rows, and a circuit arrangement for carrying out the method

Abstract: A method and device for carrying out the method for data reduction of an optoelectronic image-recording device, with the aid of autocorrelation of the individual pixel signals of each image frame, in that the difference between the present pixel signal of each pixel in an image frame and a pixel signal of the same pixel in the previous image frame, which is in each case delayed by one image frame and is updated by a factor F which is selected as a function of the relative speed between an object which is to be mapped and the image recording device, is determined and the difference is continuously added to the respective sum signal, which is likewise delayed by one image frame, and is output as a signal sequence which is related to time axes and relates to the same selected pixels of the successive image frames.