Showing papers on "Resist published in 1982"

Silicon nitride single-layer x-ray mask

Abstract: In LP‐CVD process, preparation of silicon nitride film with small tensile stress and low refractive index was investigated as a function of deposition temperature and reactant gas ratio (SiH2Cl2/NH3). The small stress film with low refractive index can be prepared easily by high temperature deposition. Applying the film to an x‐ray mask membrane, a new silicon nitride single‐layer x‐ray mask with a large area window (such as 50 mm in diameter) and high transparency to visible light is realized. Using this mask, a submicron resist pattern (0.5 μm line and space) can be replicated easily by Si–K x‐ray exposure system.

Far UV patterning of resist materials

Abstract: A technique is described for the fabrication of devices and circuits using multiple layers of materials, where patterned layers of resists are required to make the device or circuit. The fabrication process is characterized by the selective removal of portions of the resist layer by ablative photodecomposition. This decomposition is caused by the incidence of ultraviolet radiation of wavelengths less than 220 nm, and power densities sufficient to cause fragmentation of resist polymer chains and the immediate escape of the fragmented portions from the resist layer. Energy fluences in excess of 10 mJ/cm2 /pulse are typically required. The deliverance of a large amount of energy in this wavelength range to the resist layer in a sufficiently short amount of time causes ablation of the polymer chain fragments. No subsequent development step is required for patterning the resist layer.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a preferable passivation by employing an SiO2 or an Si3N4 as the first film and PSG or BPSG thinner than the first film as the second film when an interlayer insulating film of bouble layer structure of the first and second insulating films is formed on a semiconductor substrate formed with an element. CONSTITUTION:A thick field oxidized film 22 is formed on the periphery of a P type Si substrate 21, an N type region 23 is diffused in the substrate 21 surrounded by the film 22, and a thin oxidized film 24 is formed on the surface including the region 23. Then, the first wiring layer 25 is made of polycrystalline Si is formed from the end of the region 23 to the one film 22, an SiO2 film 26 forming an interlayer insulating film is formed on the overall surface. Then, with a resist film 27 as a mask it is etched, and a hole 28 is formed on the region 23. Thereafter, the film 27 is removed, a PSG film 29 of the second layer thinner than the film 27 is formed on the film 26, and a hole 32 is formed with a resist film 31. In this manner, even if an abnormally grown hillock 30 is produced on the film 29, it can be removed without passing through the lower layer film 26.

Ultrafast deep UV Lithography with excimer lasers

Abstract: The use of high-power pulsed excimer lasers for photolithography is described for the first time. Short exposure times, high resolution and absence of speckle are experimentally demonstrated. Using a XeCl laser at 308 nm and a KrF laser at 248 nm, excellent quality images are obtained by contact printing in two positive photoresists. Resolution down to 1000 line-pairs/mm is demonstrated. These images are comparable to state-of-the-art lithography done with conventional lamps; the major difference is that the excimer laser technique is ∼ 2 orders of magnitude faster. Preliminary results on reciprocity behavior in several resists are also presented.

Ion beam exposure characteristics of resists: Experimental results

Abstract: The exposure characteristics of six polymer resists to 1.5 MeV H+, He+, and O+ ions and to 20 keV electrons were measured. The resists used were polystyrene (PS), polymethyl methacrylate (PMMA), PMMA mixed with 20% of a copolymer of vinyl acetate and vinyl chloride (VMCC), poly(glycidyl methacrylate‐co‐3‐chlorostyrene) (GMC), poly(butene‐1‐sulfone) (PBS), and a novolac. The deposited energy per unit volume required to expose a resist was found to be a function of the spatial energy dissipation rate of the ion in the resist. This has been accounted for in terms of the nature of the energy distribution around the primary particle track in conjunction with whether the resist requires the activation of a single site or two adjacent sites to produce exposure.

Manufacture of semiconductor device

Abstract: PURPOSE:To remove residue in a semiconductor device by cleaning the recess formed on an insulating layer with volatile solution. CONSTITUTION:A recess formed by photolithographic technique on a semiconductor layer is cleaned with pure water, is then dried, is then cleaned with volatile solution such as xylene or the like, thereby removing a residue. It is then post-treated with butyl acetate. When thus cleaned, the residue in the previous step can be removed, and no deformation is produced at the resist, thereby performing an accurate patterning.

Intralevel Hybrid Resist Process With Submicron Capability

Abstract: A hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the < 3.0 micron geometries and optical exposure of the larger sized patterns, both sets of images are developed in a single development. Using this process, working CMOS devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 micron. The effect of E-beam dosage upon the submicron gate critical dimensions has been determined as well as other processing characteristics.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Monolithic ink jet print head

Abstract: A method of making a monolithic bubble-driven ink jet print head is provided which eliminates the need for using glue or other adhesives to construct multiple part assemblies. The concept of the method is to provide a layered structure which can be manufactured by relatively standard integrated circuit and printed circuit processing techniques. First, a substrate/resistor combination is manufactured. Then a foundation of conductive material is firmly attached to the substrate and a resist layer is used to define a perimeter/wall combination over the foundation, with the perimeter/wall combination surrounding the resistors and providing hydraulic separation between them. The perimeter/wall combination is then electroplated in place. A flash coat of metal is applied over the resist which is inside the perimeter of the perimeter/wall combination and a second layer of resist is used to define the desired orifices and the external shape of the part. A second layer of metal is then electroplated in place on the flash coat covering the first layer of resist and the perimeter/wall combination. The flash coat and resists are then stripped, leaving a void defined by the second layer of metal and the perimeter/wall combination, with this second layer of metal having an orifice therein. The void forms the firing chamber for supplying ink to the resistors during operation.

Evaluation of the gas puff z pinch as an x‐ray lithography and microscopy source

Abstract: Soft x rays (100–10 000 eV), due to their short wavelength (0.1–10 nm) can play an important role in high resolution microscopy and lithography. The gas puff Z pinch is an intense source of soft x rays. Calorimeter and x ray diode measurements showed that 10% of the stored electrical energy was converted to radiation in the range of 1–10 nm. Commercial photoresist polymethyl methacrylate (PMMA) and some new resists—CR 39, nitrocellulose, were exposed to the pinch radiation. The developed images on the resists have been studied with a scanning electron microscope. The resolution was found to be source limited, but a simple modification can improve the resolution by more than an order of magnitude.

Manufacture of semiconductor device

Abstract: PURPOSE:To simplify a complex process when an aperture for forming an emitter is drilled by a method wherein the selective etching properties of N-type and P-type polycrystalline silicon to reduce the number of masks. CONSTITUTION:After a resist pattern is left on an SiO2 layer 23, a laminated layer composed of an SiO2 layer 13, an Si3N4 layer 14, 1st polycrystalline silicon layer 15 and the SiO2 layer is patterned by RIE. After the SiO2 layer 23 is removed by an NH4F solution, 2nd polycrystalline silicon layer 16 is formed. Then, As, an N-type impurity, is diffused into the 2nd polycrystalline silicon layer 16 contacted with the 1st polycrystalline silicon layer 15 to convert a part of the 2nd polycrystalline silicon layer 16 into an N-type region 26. In this heat treatment process, boron which is added to the 2nd polycrystalline silicon layer 16 is diffused into silicon to form a diffused layer 18 for leading out the base electrode of a transistor. Then, after an SiO2 layer 33 is removed, the N-type region 26 in the 2nd polycrystalline silicon layer 16 and the 1st polycrystalline silicon layer 15 are dissolved and removed by KOH solution. Then an SiO2 layer 43 is formed on the 2nd polycrystalline silicon layer 16. The SiO2 layer 43 is formed so as to have a thickness of not less than 2000 Angstrom which is four times of the thickness of the SiO2 layer 13 in order to be sufficiently left when the SiO2 layer 13 on the region where an emitter region is to be formed is removed in a process afterwards.

Manufacture of semiconductor device

Abstract: PURPOSE:To improve quality of a semiconductor device by a method wherein size of an opening part in a spacer resist to be adhered on a bonding pad on a substrate is made as larger than the size of an opening part in a plated resist, and a part of the spacer resist is made to be buried at the circumference of the rising up part of a bump CONSTITUTION:After Al wirings 2, the bonding pad 2a are formed on the substrate 1, a protective film 3 is adhered on the whole surface, and an opening part D1 is provided on the pad 2a Moreover after the upper part of the protective film 3 is covered with the spacer resist layer 4 having the opening part D2 smaller than the D1, a barrier metal 5 is evaporated thereon Then the plating resist layer 6 having the opening part D3 larger than the D1 is adhered thereon After the bump 7 is formed, when the resist film 6, the barrier metal 5, and the spacer resist film 4 are stripped off by the lift off method, the spacer resist 4 is buried in between the bump and the protective film 3 Accordingly cushioning effect and sealing effect are exhibited, adhesion of the bump can be performed having high quality

A VLSI bipolar metallization design with three-level wiring and area array solder connections

Abstract: The ability to interconnect large numbers of integrated silicon devices on a single chip has been greatly aided by a three-level wiring capability and large numbers of solderable input/output terminals on the face of the chip. This paper describes the design and process used to fabricate the interconnections on IBM's most advanced bipolar devices. Among the subjects discussed are thin film metallurgy and contacts, e-beam lithography and associated resist technology, a high temperature lift-off stencil for metal pattern definition, planarized rf sputtered SiO 2 insulation/passivation, the “zero-overlap” via hole innovation, in situ rf sputter cleaning of vias prior to metallization, and area array solder terminals.

Semiconductor device and manufacturing process thereof

Abstract: OF THE DISCLOSURE A semiconductor device in which an insulator or conduc-tor film is closely deposited in a groove formed in a semicon-ductor substrate or an insulating or conductor layer thereon to planarize the surface thereof. A semiconductor device manufac-turing process in which a specimen is selectively etched away through using a resist pattern as a mask, a pattern forming film is deposited by a plasma deposition technique on the specimen, and the resist film is removed, whereby the pattern forming film fills up a groove formed by etching to provide a planarized surface. As the invention permits the deposition in a groove of a flat topped region which can be made coplanar with the upper surface of the substrate or layer carried on the substrate the overall height of the device can be kept small thereby increasing the packing density.

Laser assisted lift-off

Abstract: A method for selective removal of metallization in integrated circuits. A uniform metal film is applied over a patterned resist layer. A short pulse of radiant energy is then applied to the whole surface of the metal film. The resist underneath the metal film is locally heated enough to cause outgassing, which breaks the mechanical bond between the metal film and the resist. The metal film over the patterned resist layer is then removed, leaving the deposited metal film in place over areas which were not covered by the resist film.

Fabrication of isolation oxidation for MOS circuit

Abstract: A method is disclosed for fabricating an isolation oxidation (44), also referred to as field oxide, to separate the active regions on the surface of an MOS integrated circuit. On the surface of a semiconductor substrate (24) there are fabricated in successive layers an oxide layer (26), a polysilicon layer (28) and a nitride layer (30). A patterned resist layer (32) is formed on the surface of the nitride layer (30). The nitride layer (30) is etched through an opening (34) in the resist layer (32), which is then removed. The isolation oxidation (44) is then grown through an opening (36) in the nitride layer (30). The isolation oxidation (44) comprises oxide derived from the oxide layer (26) and from oxide produced from the polysilicon layer (28) and the semiconductor substrate (24). Next, the nitride layer (30), the polysilicon layer (28) and the oxide layer (26) are etched. The resulting isolation oxidation (44) has a bird's-beak area (46) which is less than 50% of the width of a bird'-beak area (14) produced using conventional MOS manufacturing processes.

Ultrafast high-resolution contact lithography with excimer lasers

Abstract: A new technique for speckle-free, fine-line high-speed lithography using high-power pulsed excimer lasers is described and demonstrated. Use of stimulated Raman shifting is proposed for obtaining the most desirable set of spectral lines for any resist. This permits, for the first time, the optimization of the exposur wavelengths for a given resist, rather than the reverse situation. Excellent-quality images are obtained in 1-µm-thick diazo-type photoresists such as ® AZ-2400 and a diazonaph-thoquinone-®Novolak resist system by means of contact printing with a XeCl laser at 308 nm and a KrF laser at 248 nm. Resolution down to 1000 line pairs per millimeter is experimentally demonstrated. These images are comparable to state-of-the-art contact lithography obtained with conventional lamps. The major difference is that the excimer laser technique is approximately two orders of magnitude faster. Tests on reciprocity failure ins everal resists indicate a decrease in sensitivity by only a factor of three, despite the ≅108 times larger power density used in the laser exposures. The possibility of photochemical reactions being diflerent from those taking place in the case of lamp exposures is discussed in view of these results.

Process for making a circuit board

Abstract: A process for making a circuit board is described in which an etching resist layer 8 is applied instead of the normal photographic treatment or screen printing for forming the conductor path pattern on the penetrating copper layer 6 of the blank. The etching resist layer 8 is vaporised by means of a laser beam, in accordance with the desired conductor path pattern, and the remaining copper layer on the points removed by the laser treatment is etched away down to the surface of the plastic board 1.

Electron beam proximity effect correction by reverse field pattern exposure

Abstract: In electron beam lithography, a beam of incident electrons exposes a preselected circuit pattern in a thin resist layer deposited on top of a substrate to be etched. Some of the electrons scatter from the substrate back into the resist layer producing an undesired exposure which produces variable resolution of features. In accordance with the disclosed technique, the region of the resist which is complementary to the desired circuit pattern is also exposed by an electron beam which has been adjusted to produce an exposure approximating that due to backscattering. This additional exposure removes the spatial variability in resolution attainable by the electron beam lithography.

Thin‐film CaF2 inorganic electron resist and optical‐read storage medium

Abstract: Polished silicon substrates were e‐gun deposited with 100‐nm films of CaF2 in a molecular beam epitaxy vacuum station. Measurements of this material system reveal a factor of 35 reduction in reflectivity for films exposed to electron irradiation. Exposure is accomplished by simply viewing the desired area using a 3‐kV Auger electron microprobe. It is further reported that this exposed inorganic material can be developed (selectively washed away) in H2O. In addition, both over and under exposures have been observed. Optimum electron exposure dose has been determined to be 0.1–0.2 C/cm2.

Process control of the chlorobenzene single-step liftoff process with a diazo-type resist

Abstract: Introduction of the single-step chlorobenzene liftoff process using a diazo-type resist to manufacturing lines produced problems not encountered during development and pilot-line work. Variances in the structure of the photoresist liftoff image are the result of complex interactions among exposure, chlorobenzene soaking, development, and post-application baking conditions. Effects produced by these variables can be controlled by monitoring the linewidth. overhang, and height of the lijtoff resist structure using a scanning electron microscope (SEMJ. Loss of resist thickness during the chlorobenzene soak is used instead of penetration, as measured on SEM photographs, to monitor the soaking process. Data are presented on the creation and stability of the overhang structure, the process controls required to achieve that stability, and the interactions among the process variables. The process, as practiced in a manufacturing mode, was found to have greatest reproduceability at low exposure, with a combination of long soaking times and high post-application baking temperatures.

Method for manufacturing a hybrid integrated circuit device

Abstract: A method for manufacturing a hybrid integrated circuit device comprising a step of forming an Al2O3 layer (22) on a metal substrate (21), a step of forming on the Al2O3 layer (22) a resist layer (23) having a pattern opposite to that of a copper layer (24) which will be formed on the Al2O3 layer (22) by a later step, a step of forming the copper layer (24) on the Af203 layer (22) using the resist layer (23) as a mask, a step of impregnating thermosetting material into both the Al2O3 layer (22) and the copper layer (24), and a step of providing at least one semiconductor element (26, 27, 28) on the copper layer (24).

A self-alignment process for amorphous silicon thin film transistors

Abstract: A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.

Manufacture of semiconductor device

Abstract: PURPOSE:To facilitate a multilayer wire by tapering the corners of an aluminum wire formed on a substrate, thereby covering the entire surface uniformly with an insulating film. CONSTITUTION:An interlayer insulating film 202 is covered on an Si substrate 201, and an aluminum wire 203 is patterned. when the surface is etched to retain the second resist layer 206 after the layer 206 is coated, the resist at the corners of the wire 203 is isolated, and the remaining part is masked with the remaining resist 206. When the aluminum wire is then etched, the wire 203 imparted with oblique sections at the corners is formed. After the resist 206 is isolated, an interlayer insulating film 204 is covered on the overall surface, and the second aluminum wire layer 205 is then formed.

Selective polysilicon oxidation technology for VLSI isolation

Abstract: Field isolation technology is described for small geometry VLSI's in which selective polysilicon oxidation is essential. The technology, also known as SEPOX, offers resist pattern reproducibility in field oxide, while maintaining crystal perfection in the substrate. By a series of experiments, high oxide reliability resulting from a white ribbon-free nature, long lifetime from C-T measurement, and small leakage currents in a reverse biased p-n junction were obtained, as well as a small geometry structure. The feasibility of this technology for MOS LSI's were examined in a 3-µm rule memory chip, and a reasonable yield and reliability were obtained. The physical limitations of SEPOX were also considered and submicrometer capability was confirmed.

Manufacture of semiconductor device

Abstract: PURPOSE:To facilitate the sorting of the proper and improper chips by coating a resist agent on a semiconductor substrate formed with a plurality of elements, exposing the substrate to form a resist film on the surface of the substrate, etching the substrate with the film as a mask and dividing it into pellets, thereby forming only the effective elements to be able to be divided. CONSTITUTION:A photoresist is coated on a wafer 8 to be scribed, and a mask pattern 9 forming a chip to be divided is formed so as to be contained in a wafer 8 in such a manner that no chip is cut at the fractional edge of the wafer. Thus, an edge which is not isolated is formed at the outer periphery of the wafer. Individual chips are scribed by etching and are isolated. In this manner, the individual chips are isolated, but only the part to become the fractional end of the outer periphery of the wafer is not divided, but is remaining in a frame shape and is simultaneously removed.

High performance electron negative resist, chloromethylated polystyrene. A study on molecular parameters

Abstract: High sensitivity and high contrast electron negative resist, chloromethylated polystyrene (CMS) was developed for direct writing electron beam lithography with 1-μm resolution. The resist shows excellent lithographic performances such as high plasma-etching durability and negligible “post polymerization effect”. A series of CMS covering a wide range of Mw, 6,800–560,000, were synthesized by the chloromethylation of nearly monodisperse polystyrenes. The effects of molecular parameters on sensitivity and resolution were investigated. The chloromethylation remarkably improved the reactivity of polystyrene, but which was saturated above 40% of chloromethylation ratio. About 100 times higher sensitivity could be achieved as compared with the starting material. As the increase of chloromethylation ratio (CR) gradually broadened the molecular weight distribution (MWD), the optimum CR was evaluated to be about 40%. In the above range of Mw, the sensitivity varies from 39 to 0.4 μC/cm, whereas the γ-value varies from 3.0 to 1.4. A sharp edge profile was obtained in developed pattern of CMS resist because of its relatively high glass-transition temperature (68–115°C) compared with commercial resists and the suitable selection of a developer. The resolution of CMS was compared with the structually related polymers synthesized from polystyrene with a broader MWD or vinylbenzylchloride and poly(chloroethylvinylether) (CEVE). These polymers show significantly lower resolution than CMS, which indicates the importance of MWD and Tg in electron negative resist.

Method and apparatus for making printed circuit boards

Abstract: Printed circuit boards are made by imaging a liquid polymer which has been coated onto the board. The imaging is accomplished while the polymer is wet with the photo tool in a close air gap relationship with the coated board. The uncured polymer which remains liquid is removed after imaging so that the board can be processed by etch resist, plate resist, or solder mask techniques. The cured polymer is removed by stripping with an alkaline solution. The apparatus consists of single station or multi-station equipment to carry out the unit operations of maintaining the board in a set position, coating with a liquid polymer, placing a photo tool in registration with the circuit board blank and in close relationship with the coating, and imaging the liquid polymer via the photo tool to cause areas of the coating to solidify and other areas to remain liquid.

Pattern forming method

Abstract: A pattern forming method for semiconductor devices in which a film layer of a compound containing silicon and nitrogen is formed between a substrate and a resist layer with a desired pattern readily formed utilizing a lift-off technique. A first film layer of a compound such as Si 3 N 4 is formed on a semiconductor substrate with a resist film layer formed in a desired pattern upon the first film layer. The first film layer is etched using the resist film layer as a mask. A second film layer is then formed on the substrate after which the first film layer is removed with an etchant which does not attack the second film layer.

The mechanism of single-step liftoff with chlorobenzene in a diazo-type resist

Abstract: The mechanism of the chlorobenzene single-step liftoff process is defined. The chlorobenzene penetrates to some depth into the resist film during the soaking cycle, extracting residual casting solvent and low-molecular-weight resin species. The chlorobenzene is subsequently removed by a rinse cycle. The penetrated layer of resist develops at a slower rate than the underlying bulk resist, producing the liftoff structure.

New inorganic electron resist system for high resolution lithography

Abstract: A new Ag2S/As2S3 negative electron resist system is proposed for nanostructure fabrication. Linear gaps down to 30 nm wide have already been resolved. Sensitization of the Ag2S3 with a chemically deposited layer of Ag2S overcomes the limitations involved in the use of silver halides as a source of silver. Although the sensitivity of this resist is very low (4×10−3–10−2 C/cm2) its extremely high contrast (γ>5.5) is an advantage in nanostructure fabrication where it is necessary to discriminate against exposure by backscattered electrons.