Showing papers on "Resist published in 1987"

Development of Positive Photoresists

Abstract: A mechanism for the development of positive optical photoresists is proposed, leading to the derivation of a development rate equation. This rate equation compares favorably with experimentally determined development rates. Typical values of the rate constants involved are given. Empirical models are given for the surface induction and substrate adhesion effects. An overall positive resist processing model requires a mathematical representation of the development process. Previous attempts have taken the form of empirical fits to development rate data as a function of exposure (1, 2). The model formulated below begins on a more fundamental level, with a postulated reaction mechanism which then leads to a development rate equation. The rate constants involved can be determined by comparison with experimental data. Deviations from the expected development rates have been reported under certain conditions at the surface of the resist and near the resist-substrate interface. These effects, called the surface induction and substrate adhesion effects, respectively, can be related empirically tothe expected development rate, i.e., to the bulk development rate as predicted by a kinetic model. Bulk Development Model In order to derive an analytical development rate expression, a kinetic model of the development process will be used. This approach involves proposing a reasonable mechaffism for the development reaction and then applying standard kinetics to this mechanism in order to derive a rate equation. We shall assume that the development of a diazo-type positive photoresist involves three processes: diffusion of developer from the bulk solution to the surface of the resist, reaction of the developer with the resist, and diffusion of the product back into the solution. For this analysis, we shall assume that the last step, diffusion of'the dissolved resist into solution, occurs very quickly so that this step may be ignored. Let us now look at the first two steps i n the proposed mechanism. The diffusion of developer to the resist surface can be described with the simple, diffusion rate equation rD = k,~(D - Ds) [1] where rD = rate of diffusion of the developer to the resist surface,. D = bulkdeveloper concentration, Ds = developer concentration at the resist surface, and kD = rate constant. We shall now propose a mechanism for the reaction of developer'with theresist. The resist is composed of large macromolecules of resin R along with a photoactive compound M, which converts to product P upon exposure to UV light. The resin is quite soluble in the developer solution, but the presence of the PAC (photoactive compound) acts as an. inhibitor to dissolution, making the development rate very slow. The product P, however, is very solubie in developer, enhancing the dissolution rate of the resin. Let us assume that n molecules of product p react with the developer to dissolve a resin mo'lecule. The rate of the reaction is rR = - kRDsP '~ [2] where rR = the rate of reaction of the developer with the resist and kR = rate constant. From the stoichiometry of the exposure reaction P = M,, - M [3]

Point exposure distribution measurements for proximity correction in electron beam lithography on a sub‐100 nm scale

Abstract: The exposure distribution function in electron beam lithography, which is needed to perform proximity correction, is usually simulated by Monte Carlo techniques, assuming a Gaussian distribution of the primary beam. The resulting backscattered part of the exposure distribution is usually also fitted to a Gaussian term. In this paper we demonstrate a technique, using a very high contrast resist, whereby the normalized point exposure distribution can be measured experimentally, both on solid substrates which cause backscattering, and on thin substrates where backscattering is negligible. The data sets so obtained can be applied directly to proximity correction and represent the practical conditions met in pattern writing. Results are presented of the distributions obtained on silicon, gallium arsenide, and thin silicon nitride substrates at different beam energies. Significant deviations from the commonly assumed double Gaussian distributions are apparent. On GaAs substrates the backscatter distribution cannot adequately be described by a Gaussian function. Even on silicon a significant amount of exposure is found in the transition region between the two Gaussian terms. This deviation, which can be due to non‐Gaussian tails in the primary beam and to forward scattering in the resist, must be taken into account for accurate proximity correction in most submicron lithography, and certainly on the sub‐100 nm scale.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the damage to a gate insulating film by removing a resist film by dry etching, in the condition that a not patterned first insulating film is covered with a conductive layer CONSTITUTION:The surface of an Si wafer 1 is coated with an oxide film 2, and thereon a polysilicon layer 3 is made Then, by CVD method, the obverse and the reverse of the polysilicon layer 3 overlaid on the Si wafer 1 are covered with a nitride film 7 And a resist film 4 is made in the specified region on the nitride film 7 above the surface of the Si wafer 1 Next, with the resist film 4 as a mask, the nitride film 7 is dryetched, thus only the nitride films 7 on the gate electrode formation area at the surface of the Si wafer 1 and on the reverse of the Si wafer 1 are left Then, by oxygen plasma, the resist film 4 is all removed from the surface At this time, since the surface of the oxide film 2 being a conductive material is covered with a polysilicon film 3, the plasma damage to the oxide film 2 by oxygen plasma is prevented

Ion Beam Lithography

Abstract: Apparatus and method for projection ion beam lithography are described which allow formation of low distortion, large field, reduced images of a mask pattern at a wafer plane using an optical column of practical size. The column shown is comprised of an accelerating Einzel lens followed by a gap lens, with numerous cooperating features. By coordinated selection of the parameters of the optical column, lens distortion and chromatic blurring are simultaneously minimized. Real time measurement of the position of the image field with respect to the existing pattern on the wafer is employed before and during the time of exposure of the new field and means are provided to match the new field to the existing pattern even when the latter has been distorted by processing. A metrology system enables convenient calibration and adjustment of the apparatus.

Method of forming pattern and projection aligner for carrying out the same

Abstract: An area on a photoresist film which is formed on a substrate surface having a topography, is exposed a plurality of times in such a manner that the image plane of a mask pattern is formed at a plurality of positions which are spaced apart from a reference plane in the substrate in the direction of an optical axis, and then the photoresist film is developed to form a resist pattern. According to the above method, the effective focal depth of the projection aligner used is enhanced, and moreover the reduction of the image contrast at the photoresist film is very small by the plural exposure operations. Accordingly, a fine pattern can be formed accurately on the substrate surface having the topography.

Negative resist material

Abstract: A negative resist material consists of poly (silsesquioxane) of weight average molecular weight 2000 or more represented by the general formula (1): (CH.sub.2 ═CHCH.sub.2 SiO.sub.3/2).sub.m (ClCH.sub.2 SiO.sub.3/2).sub.n (1) where m and n denote the molar percentages of each component of the polymer, and m+n=100. A method of producing such a resist material and a method of forming a bi-layer resist pattern using the resist material are also disclosed.

Process for forming sub-micrometer patterns using silylation of resist side walls

Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions. First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.

Method of producing conductor circuit boards

Abstract: A thin metal layer is formed by electrolysis (S2) maintaining a thickness of 1 to 5 mum on an electrically conductive single-plate substrate having a predetermined coarseness, a resist mask is formed (S3) on the surface of the thin metal layer, and then a conductor circuit is electroformed thereon (S4) using copper. After the surface of the conductor circuit is coarsened (S5), the conductor circuit is laminated on an insulating substrate for each single plate via the thin metal layer and is intimately adhered in a unitary structure by the application of heat and pressure (S7). Then, the single plate only is peeled off (S8), and the exposed thin metal layer is removed by etching (S9). The thin metal layer and the conductor circuit are electroplated at high speeds under the conditions of a liquid contact speed of 2.6 to 20 m/sec. and a current density of 0.15 to 4.0 A/cm2, so that a required intimate adhesion force is obtained between the thin metal layer and the resist mask. Further, the conductor circuit is provided with flexibility like that of rolled and annealed copper, thus making it possible to produce very thin and high-density conductor circuits having a thickness of smaller than 10 mum adapted not only to rigid printed wiring boards but also to flexible printed wiring boards.

Polymer Materials for Microlithography

Abstract: Since the last review on resist materials for microlithography appeared in the Annual Review of Materials Science (Vol. 6, 1976) (1), astonishing progress has been made in microelectronics, especially in the technology of lithography used to generate high-resolution patterns. In 1976, the state­ of-the-art dynamic random access memory (DRAM) device was capable of storing 4000 bits of data and had minimum features of 5-6 flm. Photo­ lithography was utilized to pattern these devices using either contact print­ ing or, the then relatively new, one-to-one projection printing. Today, devices with one million bits of storage capacity are commercially available with minimum features of 1.0 flm (2). By 1976 standards, it is surprising that photolithography is still the technology used to fabricate micro­ electronic chips. Step-and-repeat 5 or 10 x reduction cameras and highly sophisticated I -toI projection printers are the dominant printing tech­ nologies. There is perhaps no better example than lithography to illustrate the uncertainty associated with predicting technological direction and change. In 1976, it was generally believed (though not by everyone) that photolithography would not be able to produce features smaller than about l.5 flm with high chip yields in a production environment. The current belief is that conventional photolithography will be able to print 0.6-0.8 flm features and will be the dominant technology well into the first half of the 1990s. The same basic positive photoresist, a diazonaphtho­ quinone-novo lac composite, will likely still be the resist of choice. The cost of introducing a new resist material and the cost associated with new hardware are strong driving forces pushing photolithography to its absolute, ultimate limits.

A practical trench isolation technology with a novel planarization process

Abstract: We develop a new vertical-trench isolation method that utilizes a thin SiO 2 film in-between double photoresists for uniform top-resist coating and for an etch-back barrier, a poly-silicon film above active regions for an etch-back buffer and large tilt-angle boron ion implantations into the trench-sidewalls for narrow channel effect control. The Planarization with the Resist / Oxide / Resist and the Poly _Silicon (PRORPS) can isolate the whole surface of a 6 inch-diameter wafer very uniformly with a large process margin. The standard deviation of the threshold voltage of a n-channel MOS-FET (W/L= 10µm/0.8µm) over the whole wafer is 0.38 % at about 0.6 V threshold voltage. The narrow-channel-effect is controlled for FET's down to 0.5 µm channel width. The method is applied to the megabit SCC (Surrounded Capacitor Cell) DRAM developed here and the cells and the peripheral-circuits are isolated at the same time successfully.

Exposure of calcium fluoride resist with the scanning tunneling microscope

Abstract: The scanning tunneling microscope (STM) can be used to generate very fine beams of very low energy electrons (below 100 eV). Under optimum conditions the beam diameter is proportional to beam voltage and hence, when using such a beam as an exposure tool it is desirable to employ the thinnest possible resists. The metal halides in general have several properties that make them attractive candidates for use in a scanning tunneling microscope. They are easily evaporated as thin films of thickness from 10 to 100 nm. It is important that an insulating resist film be thin so that the electrons can penetrate it and the tip does not crash into it. Thicker films require a higher accelerating voltage and this degrades resolution. The sensitivity of the metal halides is on the order of 1 C/cm2, which coincides with the dose range most readily obtainable in our instrument. Finally, the exposure voltage threshold of the metal halides is thought to be in the range of a few tens of volts. This is low enough to take adva...

Bilayer photoresist process

Abstract: The present invention relates to a bilayer photoresist process, wherein a first planarizing resist layer is applied to a base and a second or top photoresist layer is applied over the first. The top layer resist is sensitive to deep UV light, while the planarizing layer resist is sensitive to near UV or violet light. The top layer, by use of a dye or other means, is opaque to predetermined near UV or violet wavelengths by which the planarizing layer is illuminated. The top layer is patterned using deep UV light. A flood exposure of the predetermined near UV or violet wavelengths is then used to transfer the pattern of the top layer to the bottom planarizing resist layer. Improved resolution is achieved by the use of deep UV light for patterning the top layer. Less costly yet faster illumination of the planarizing layer is accomplished by using near UV or violet light. Additionally pattern degradation due to spurious reflections normally occurring from near UV exposure of the top layer is avoided. Also, the near UV sensitive resist planarizing layer results in a better dry etch mask than previous bilayer scheme planarizing layers. The pattern of the resolution layer can be transferred to the planarization layer by plasma etching.

Focus: The critical parameter for submicron lithography

Abstract: A simple model of the photolithographic process is used to analyze the effects of defocus on resist profiles and process control. An expression is obtained for linewidth variation as a function of exposure and defocus, whereby a process window can be established. The parameters which must be specified in a practical and self‐consistent definition of the depth of focus are identified: the resist process, printdown, nominal linewidths, linewidth variability, and profile slope. The model also provides a framework for interpreting empirical results obtained on a new generation of wafer steppers. Measurements of the effects of lens astigmatism and barometric pressure on the depth of focus are presented.

Compressed fluid technology: Application to RIE‐developed resists

Abstract: A novel plasma-developed resist lithographic process is described that uses compressed CO2 to extract nonvolatile siloxane molecules from host organic polymers. The process is capable of at least 0.75 μm resolution with an X-ray sensitive guest siloxane-host polymer system. A processing window was investigated and defined to eliminate or minimize film damage during compressed fluid extraction. Polymer deformation was usually avoided by using supercritical CO2 rather than liquid CO2, provided that film thicknesses were ≤1 μm. Increased solute concentrations in the host polymer also adversely affected the quality of extracted films. An in situ capacitance process monitoring scheme was developed which indicated that film damage, when observed, was primarily caused by explosive decompression of the solvent from the host polymer.

Current‐density profiles for a Ga+ ion microprobe and their lithographic implications

Abstract: A 50‐keV focused Ga+ beam was used to expose dots in a negative‐acting bilevel resist structure in an exposure range between 1 μs/pixel and 4 s/pixel. The radii of the resist dots were used to determine the current‐density profiles of the Ga+ ion microprobe down to six orders of magnitude below the peak versus system magnification and ion source current. The effect of the beam profile on the limiting pitch for densely packed resist dot arrays was modeled and compared to experimental results.

Progress in self‐developing metal fluoride resists

Abstract: Thin films of metal fluorides such as AlF3, FeF2, CrF2, CsF, LaF3, BaF2, and SrF2 have been used as electron beam sensitive resists. When exposed in an ultrahigh vacuum system by a high intensity electron beam at line doses of 0.5 to 400 μC/cm at 100 keV on a thin membrane substrate, the films act as positive resists. At line doses of typically an order of magnitude less than in the case of the positive resist mode, the films also act as negative resists requiring the use of an appropriate developer. The exposure properties for these metal fluoride resists are discussed along with their film properties, sensitivity, and etching characteristics.

Top imaged resists

Abstract: The present invention is concerned with methods of converting a single resist layer into a multilayered resist. The upper portion of the single resist layer can be converted into a dry-etch resistant form. The conversion can be a blanket conversion of the upper portion of the resist layer or can be a patterned conversion of areas within the upper portion of the layer. A patternwise-converted resist can be oxygen plasma developed. The upper portion of the single resist layer can be patternwise converted into a chemically different composition or structure having altered absorptivity toward radiation. The difference in radiation absorptivity within the patterned upper portion of the resist enables subsequent use of blanket irradiation of the resist surface to create differences in chemical solubility between areas having the altered absorptivity toward radiation and non-altered areas. The difference in chemical solubility enables wet development of the patterned resist.

Method of manufacturing photo-mask and photo-mask manufactured thereby

Abstract: A method of manufacturing a photo-mask, which includes the steps of applying a resist film (3) onto a substrate (1) of quartz, glass and the like, subjecting the resist film (3) to light exposure and development to form a fine resist pattern (4), etching the mask substrate (1) covered by the fine resist pattern (4) so as to cause a non-light transmitting thin film (2) of Cr, Ta, etc. to adhere thereon by vapor deposition, sputtering and the like, and removing the thin film (2) on the resist pattern (4) together with the resist film (3), thereby to form the photo-mask. The disclosure is also directed to a photo-mask manufactured by the above method.

Attainment of 0.13‐μm lines and spaces by excimer‐laser projection lithography in ‘‘diamond‐like’’ carbon‐resist

Abstract: Recent results are reported for the use of ‘‘diamond‐like’’ hard carbon as a photoresist for excimer‐laser projection lithography. Well resolved 0.13 μm lines and spaces have been achieved using 193 nm radiation and reflective optics.

Process for forming planar chip-level wiring

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface (10) is provided a dual layer of an insulator (14) and hardened photoresist (16) having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer (22) of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist (28, 30) is formed filling the metal valleys and obtaining a substantially planar surface (32). The lower component layer (28) is thin and conformal and has a higher etch rate than the upper component layer (30) which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photo-resist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photo-resist sacrificial layer.

Selective backside plating of gaas monolithic microwave integrated circuits

Abstract: A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

Dot lithography for zero‐dimensional quantum wells using focused ion beams

Abstract: A 50‐keV focused Ga+ beam formed in a two‐lens microprobe column with prefinal lens deflection was used to expose dot arrays in a negative acting bilevel resist. Dot arrays 600 μm×600 μm with 600‐A‐diam resist posts on 0.6 μm centers (incorporating 1024×1024 dots) were fabricated with ion exposure times of 18 s. By reducing the beam dwell time by a factor of 2, roughly 300‐A‐diam posts were fabricated. Since the ions stop in the bottom resist layer and do not enter the substrate, the optical properties of underlying material should not be altered by damage from the exposure process.

Dry etching method

Abstract: PURPOSE:To enhance the accuracy of a dry etching method by pretreating a resist film formed with an etching pattern with gas of CF4+H2, and dry etching it according to the resist pattern. CONSTITUTION:A resist film 13 is formed on an aluminum film 12 formed on a semiconductor substrate 11, and a hole 14 corresponding to the etching portion is formed at the film 13. Then, a pretreatment with reaction gas of 'CF4+H2' is executed. A post baking is performed, and the film 12 is dry etched. Thus, since the selection ratio of a material to be etched and the resist can be set sufficiently largely, the dry etching of high accuracy can be achieved.

Monte Carlo Methods and Microlithography Simulation for Electron and X-Ray Beams

Abstract: Publisher Summary This chapter reviews the Monte Carlo (MC) simulation of electron scattering and its various applications to microlithography. This simulation is also useful for x-ray lithography, where photoelectrons and Auger electrons are produced by x-ray beams. To investigate the ultimate spatial resolution of electron-beam lithography, the electron energy loss is treated by two discrete processes: inner- and outer-shell electron excitations. One characteristic feature of MC calculations is the ease of setting geometrical boundary conditions by changing the input data, such as incidence angle, or by programming a special specimen geometry. In the electron-beam lithography, various types of geometry can be encountered depending on the fabrication process technologies. One of the most important geometries is that of a thin resist film on a thick substrate. The MC programs are developed to take account of this special geometry. There are two ways to take account of the beam size in an MC simulation. One is to begin from the MC calculation of the absorbed energy distribution, f o (r) or f 0 (x) for an ideal point or line source, respectively. The other way is to include the beam distribution at the initial stage of the MC simulation.

Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures

Abstract: A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.

Dual glass contact process

Abstract: A method for forming contact openings in semiconductor devices. In borosilicate glass layers deposited over the gate and drain area of a device, followed by a borophosphosilicate glass layer. After masking with photoresist and defining openings, the borophosphosilicate glass is isotropically etched to undercut the resist layer. A plasma etch is utilized to anisotropically etch the borosilicate glass layer and expose the surface of the drain area. After the photoresist is stripped away, a reflow step is employed to reduce the sharp edges of the glass layer and result in a sloped contact opening profile. Good metal coverage is achieved while maintaining isolation of the gate.

Apparatus for detecting faults on the surface of a resist master disc and measuring the thickness of the resist coating layer

Abstract: An apparatus for detecting faults on the surface of a resist master disc and for measuring the thickness of the resist coating layer includes a single light source for generating a laser beam for inspection of the master disc, a first separator for separating the laser beam into a first laser beam which is used for the detection of faults, and a second laser beam which is used to measure the thickness of the resist coating layer. The second laser beam is further separated into two laser beams one of which is irradiated on the surface of the resist coated master disc at a given angle of incidence. The detection of faults on the surface of the master disc is performed by detecting a level change of the quantity of reflection light of the first laser beam from the resist master disc, and the measurement of the thickness of the resist layer is performed by using a ratio between quantities of two laser beams obtained from the second laser beam one of which is detected after being reflected by the surface of the resist master disc.

Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate

Abstract: A new method for two-dimensional (2D) photolithography simulation is proposed. Lightwaves in photoresist are assumed to be polarized, and the layer beneath the photoresist is assumed to be a perfect conductor. In order to analyze lightwave behavior in a 2D region, Maxwell equations for electromagnetic fields are simplified into a Helmholtz equation which is solved in the photoresist region, taking lightwave damping in the infinite vacuum region surrounding the photoresist into account. The finite-element method and boundary-element method are used in the calculations. The bleaching model proposed by Drill et al. is applied to describe photoresist behavior on irradiation by exposure light. When this simulation is applied to a photoresist system on a reflective stepped surface, the simulated photoresist image is found to be in reasonably good agreement with an actually developed profile.

Organosilicon deep UV positive resist consisting of poly(p‐disilanylenephenylene)

Abstract: A new class of positive deep ultravoilet (UV) resists consisting of poly(p-disilanylenephenylene)s was developed, in which a disilanylene unit and a phenylene unit are connected alternatively in the polymer main chain. These resists had very high etching resistance against oxygen plasma. The lithographic applications of a double-layer resist system in which the poly(p-disilanylenephenylene) film was used as the top imaging layer were examined. As a result, very high resolution and high contrast were attained. The double-layer resist technique using organosilicon deep UV positive resist appears very promising for lithographic applications.

Method of producing the gate electrode of a field effect transistor

Abstract: A method of forming a self-aligned gate electrode of a field effect transistor, in which a resist pattern is formed on a substrate by lithography, an ion-implanted layer in the substrate at the side of the resist is formed by ion implantation, an insulating film is formed on the substrate by electron cyclotron resonance plasma chemical vapor deposition, the resist pattern and a part of the insulating film on the resist pattern removed by lift-off to thereby form an insulating pattern with an opening, the substrate annealed to activate said ion-implanted layer and a gate electrode formed in the opening by a spacer lift-off method.