Showing papers on "Resist published in 1991"

Selective plating method for forming integral via and wiring layers

Abstract: In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

Rippled polysilicon surface capacitor electrode plate for high density dram

Abstract: A new method to produce a microminiturized capacitor having a regular microscopic ripple surface electrode is achieved by depositing a first polysilicon layer over a suitable insulating base. A resist layer is formed over the first polysilicon layer. The resist layer is exposed through a mask having a pattern of regular spaced openings in the areas of the planned capacitor to radiant energy in sufficient quantity to under expose, out of focus expose or a combination of under expose and out of focus expose the resist layer. The mask is shifted a fixed and short distance. The resist layer is exposed through the shifted mask to radiant energy in sufficient quantity to under expose or out of focus expose, or a combination of under expose or out of focus expose the resist layer again and in a different location. The shifting of the mask and exposing resist steps are repeated until a pattern of the regular microscopic ripple has been formed in the resist layer. The resist layer is developed to leave the pattern of regular microscopic ripple in the surface of the resist layer. The resist layer and said first polysilicon layer is uniformly and anisotropically etched to create the pattern of regular microscopic ripple in the surface of the first polysilicon layer. The remaining resist layer is removed. An insulating layer is deposited over the ripple surface. The capacitor structure is completed by depositing a second polysilicon layer over the insulating layer.

Airborne chemical contamination of a chemically amplified resist

Abstract: We have found that the performance of the t-BOC/onium salt resist system is severely degraded by vapor from organic bases. This effect is very pronounced and can be observed when the coated wafers stand for 15 minutes in air containing as little as 15 parts per billion (ppb) of an organic base. The observed effect, caused by this chemical contamination, depends on the tone of the resist system. For negative tone systems the UV exposure dose, required to obtain the correct linewidth, increases. While for the positive tone system, one observes the generation of a skin at the resist-air interface. Both effects are caused by the photogenerated acid being neutralized by the airborne organic base. There are a wide variety of commonly used materials which can liberate trace amounts of volatile amines and degrade resist performance. For example, fresh paint on a laboratory wall can exhibit this detrimental effect. These effects can be minimized by storing and processing the resist coated wafers in air that has passed through a specially designed, high efficiency carbon filter. The implementation of localized air filtration, to bathe the resist in chemically pure air, enabled this resist system to operate in a manufacturing environment at a rate of 100 wafers/hour.

Method for forming a dielectric thin film or its pattern of high accuracy on a substrate

Abstract: A method and apparatus for forming a dielectric thin film or pattern thereof is provided in which a positive or negative resist of a desired pattern if formed on various substrates including a semiconductor substrate by contact of the resist with a liquefied gas or super critical fluid of CO2, NH3 or the like. Alternatively, a thin film of an organic or inorganic compound dissolved or dispersed in an organic solvent which has been formed on substrate becomes substantially free of any organic matter or functional groups by contact with the liquefied gas or super critical fluid. Semiconductor devices of high performance and high reliability are ensured.

Method for forming patterned films on a substrate

Abstract: A method of forming patterned films on a semiconductor substrate 10 includes the steps of depositing a hardened photo resist underlay 30 onto the substrate, then depositing a polyether sulfone release layer 32, then depositing a photo sensitive resist layer 34 and exposing an etching a metallization pattern 36, 38 to the substrate 10. The structure is then blanket deposited with a conductive layer 40 to thereby create a conductive contact stud 42. The film layer 40 and resist layer 34 are removed by dissolving the polyether sulfone layer 32 in an NMP solution and the photo resist underlayer 30 is then removed using a selective photo resist stripper composition.

Process for forming fine pattern

Abstract: In a process using a single-layer or multi-layer resist, by using a resist material comprising an acid-decomposable polymer, an acid generator and a conducting polymer or a resist material comprising a monomer to be made reactive by an acid, an acid generator and a conducting polymer, there can be formed a fine pattern precisely without inviting charging during charged beam writing.

Manufacture of semiconductor device

Abstract: PURPOSE:To suppress the deterioration of a gate oxide film by a method wherein a gate is formed on a substrate and thereafter, silicon is implanted in drain regions for N layer formation and a polysilicon region and after this, an impurity for drain formation is implanted and the impurities are electrically activated in such a way as to perform a heat treatment. CONSTITUTION:Boron is channel-doped to a silicon substrate 1 and thereafter, a gate oxide film 2 is formed. Then, a polysilicon film 3 is deposited and the films 2 and 3 located at regions other than a gate are removed by etching. After this, a resist 5 is deposited on regions other than regions, where are used as drain regions 6 for N layer formation, and the gate region and silicon is implanted in the regions 6 for N layer formation and the polysilicon region using this resist 5 as a mask. Then, the resist 5 is removed, an oxide film 4 is formed on the gate and arsenic is ion- implanted using this film 4 as a mask to form N layer. After this, after an oxide film is deposited, sidewalls 9 are formed by anisotropic etching and arsenic is implanted to form N layers 8. After this, each impurity enters the position of the lattice of a silicon crystal by a heat treatment and is electrically activated. Thereby, gentle concentration distributions can be respectively obtained from a channel region toward the drain layers.

Silica-based anti-reflective planarizing layer

Abstract: There is disclosed a dyed, spin-on glass composition with a high carbon content for use in providing antireflective planarizing layers on substrates such as semiconductor silicon wafers. These layers can be used as hard masks by etching patterns therein. These hard masks can be used in multilayer resists and in making lithography masks. Methods for producing these hard-masks are also provided.

Nucleation control of diamond films by microlithographic patterning

Abstract: A high temperature resist process is combined with microlithographic patterning for the production of materials, such as diamond films, that require a high temperature deposition environment. A conventional polymeric resist process may be used to deposit a pattern of high temperature resist material. With the high temperature resist in place and the polymeric resist removed, a high temperature deposition process may proceed without degradation of the resist pattern. After a desired film of material has been deposited, the high temperature resist is removed to leave the film in the pattern defined by the resist. For diamond films, a high temperature silicon nitride resist can be used for microlithographic patterning of a silicon substrate to provide a uniform distribution of diamond nucleation sites and to improve diamond film adhesion to the substrate. A fine-grained nucleation geometry, established at the nucleation sites, is maintained as the diamond film is deposited over the entire substrate after the silicon nitride resist is removed. The process can be extended to form microstructures of fine-grained polycrystalline diamond, such as rotatable microgears and surface relief patterns, that have the desirable characteristics of hardness, wear resistance, thermal conductivity, chemical inertness, anti-reflectance, and a low coefficient of friction.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a sufficient element isolation characteristic and a stable device characteristic by a method wherein a higher-concentration channel stop implantation operation is executed for an element isolation region formed by a minimum design rule as compared with an element isolation region whose design rule is not strict CONSTITUTION:A pad oxide film 2 is formed on a P-type silicon substrate 1; in addition, a nitride film 3 is deposited; after that, an opening part of, eg 05mum is formed in a part to be used as an element isolation region of a memory cell part, a sense amplifier part and a decoder part A region other than the memory cell part, the sense amplifier part and the decoder part is 10mum which is thicken than 09mum by a design rule Then, a resist is removed; after that, only a region with an opening width of 05mum is opened; other regions are masked with a resist 4; borons are implanted by using the resist as a mask under conditions of an accelerating voltage of 25keV and a dose of 7X10 cm Then, the resist is removed; after that, only the region with the opening width of 05mum is masked with the resist 4; borons are implanted under conditions of an accelerating voltage of 25keV and a dose of 4X10 cm

Method for forming semiconductor device isolating regions

Abstract: A method for forming semiconductor device isolation regions including steps of forming a first insulating film on a semiconductor substrate, removing the first insulating film in a portion to become a device isolation region with use of a resist pattern formed in a one-time lithography step as a mask so as to form an opening which reaches the semiconductor substrate, removing the resist pattern to deposit a second insulating film on the first insulating film and the inside of the opening and then etching the entire surface in order to make the second insulating film remain on only the periphery of the bottom of the opening and to expose the surface of the semiconductor substrate in a central portion of the bottom of the opening, forming an oxide film on the surface of the semiconductor substrate exposed in the central portion of the bottom of the opening with use of the first insulating film and the second insulating film on the periphery of the bottom of the opening as a mask by a selective oxidation method, removing the second insulating film on the periphery of the bottom of the opening and then etching the surface of the semiconductor substrate exposed on the periphery of the bottom of the opening with use of the oxide film formed in the central portion of the bottom of the opening by the selective oxidation method and the first insulating film which remains in portions other than the device isolation region as a mask so as to form a trench, and burying the trench with a third insulating film.

Determination of acid diffusion in chemical amplification positive deep ultraviolet resists

Abstract: A new method was developed to study the diffusion of photogenerated acid in chemical amplification resist systems which allowed an estimation of the diffusion range by simple means. The acid mobility was investigated for two different resist systems under various process conditions. It was found that solvent traces in the film cause a very strong increase of the acid mobility. In order to control the diffusion range, the post‐exposure‐bake temperature must be below the glass transition temperature. For one resist system, the increase in resist sensitivity with increasing baking temperature was much smaller than the corresponding increase in diffusion range. The results corresponded well with those obtained by lithography with the same resist.

Detection and printability of shifter defects in phase-shifting masks

Abstract: Because of the high printability of shifter defects in phase-shifting masks, it is worthwhile to characterize the inspection and printing of the shifter defects. The detectability and printability of shifter defects as a function of size and location have been investigated by experiments and simulation. A test mask with various programmed shifter defects was inspected by means of a die-to-die inspection system and printed in positive resist with an i-line stepper. Corner defects are difficult to detect and have low printability. A defect located in small features has high printability. We have also investigated the detectability and printability of the phase angle defects which have phase angles other than 180°. Defects with 120° to 180° phase angles have high printability. Defects with phase angles below 90° are not printed.

Method and apparatus for fabrication of thin film semiconductor devices using non-planar, exposure beam lithography

Abstract: An apparatus and method for the nonplanar treatment of a volumetric workpiece or substrate utilizing exposure beam lithography are disclosed. The method includes supplying one or more layers of one or more semiconductor materials to surfaces of the substrate, applying a resist over the semiconductor layers, setting the resist, and then directing an exposure beam, such as an electron beam, toward the substrate. The substrate is then moved in at least two degrees freedom of movement, relative to the beam, with one degree of freedom of movement being the rotating of the substrate about an axis generally perpendicular to the beam. The other degree of freedom of movement could be moving the substrate linearly in a direction generally parallel to the axis. By such movement, the resist is exposed to the beam in a predetermined pattern. The exposed resist is then developed and a layer or layers under the exposed resist are etched. The remaining resist is then removed yielding the desired semiconductor device.

Manufacturing method for a multilayer printed circuit board

Abstract: Disclosed is a method for manufacturing a multilayer circuit board in which landless inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate. The method of the invention utilizes a single photoresist to form a circuitization layer and the conductive via extending upwardly from it. In the method of the invention a metal layer is applied to the substrate, and photoresist is applied to the metal layer. The photoresist is then exposed and developed to define a resist hole. A via bump is formed in the resist hole. The residual resist is then imaged to form a first circuit pattern in the underlying metal layer. The remaining photoresist is removed from the first metal layer, and an organic dielectric layer is formed on the etched metal layer, the exposed substrate, and via bump. The organic dielectric layer is then flattened or otherwise processed to expose the surface of the via bump. Either a second metal layer or an electronic part is deposited or applied to the exposed top surface of the via bump as an upper-layer electric circuit element.

Phase-shifting photolithography applicable to real IC patterns

Abstract: A phase-shifting technique which simplifies mask fabrication and is applicable to actual IC patterns has been introduced into the i-line positive resist process. It combines edge-contrast enhancement and a chromeless mask. Although the effect of this technique on line and space patterns has turned out to be more restricted than that of the alternating mask technique, it can improve exposure and focus latitude in isolated hole patterning. The authors report on their estimation of the optimum shifter width which maximizes contrast enhancement on lines and spaces as well as on isolated hole patterns. Experimental data is presented to verify the improvements in photolithographic performance of isolated hole patterning due to this technique.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

100 nm wide copper lines made by selective electroless deposition

Abstract: Copper lines with a minimum width of 100 nm were fabricated by selective electroless copper deposition (SED). The deposition reaction is based on the neutralization of positive copper ions in a basic solution by electrons which are the result of the reaction between formaldehyde and the hydroxyl ions. The reduction reaction requires a high pH typically in the range of 11.5-13 at the deposition temperature which is between 55 degrees C and 70 degrees C. The high pH required for the deposition reaction is achieved either by using alkaline bases, like sodium-hydroxide, or alkaline-free bases, like tetramethylammonium hydroxide (TMAH). Experimental data show similar results for both alkaline and alkaline-free deposition solutions. The copper nanolines were produced using electron beam lithography and polymethylmethacrylate (PMMA) e-beam resist due to its compatibility with the high pH of the deposition solution. The first approach, which is described here for making copper nanolines, produced 100 nm wide lines with vertical side walls and aspect ratio (height/width) as high as 4:1. The lines were uniform over both small and large areas and the deposition was only on the pre-designated regions (i.e. full selectivity). A second fabrication technique, which is also described, formed a fully-planar topography in which the copper is buried in an interlevel dielectric. 150 nm wide copper lines buried in 250 nm deep trenches in chemically-vapor-deposited (CVD) silicon-dioxide were made using that technique. Both techniques are described in detail and experimental results are presented in the form of SEM pictures. Selective copper deposition introduces some new problems in general and there are also some particular problems that are associated with the techniques described. Specific problems, such as step coverage and copper line shapes are discussed as well as more general problems like the compatibility with integrated circuit manufacturing technology.

Subhalf-micron gate GaAs MESFET process using phase-shifting-mask technology

Abstract: For the purpose of an ultra-high-speed GaAs LSI, the phase-shifting-mask technology has been applied to the fabrication process of subhalf-micron gate GaAs MESFETs. The lithography of gate pattern was performed by the PEL (phase-shifter edge-line) mask technique with the double exposure process using the i-line stepper, where the resist spacing was precisely controlled by the exposure dose. The gate metal of W-Al was then etched by ECR plasma with no under-cut, which resulted in fine gate patterning. GaAs MESFETs fabricated in a 3-inch wafer have shown a good uniformity of Vth as small as 40 mV, and a high gm property of 424 mS/mm with a good uniformity of gm (3.5%) at the gate length of 0.22 mu m. >

Sub‐30 nm lithography in a negative electron beam resist with a vacuum scanning tunneling microscope

Abstract: We report studies of minimum feature sizes in 50 nm films of the high‐resolution negative electron beam resist, SAL‐601‐ER7 from the Shipley Corporation. Developed linewidths of 27 nm and line spacing of 55 nm, from center to center, were produced by lithography with a vacuum scanning tunneling microscope (STM). In contrast, a minimum linewidth of 95 nm was obtained from exposure with a 17 nm (1/e diameter) 50 kV electron beam. Patterns written in the STM at electron energies down to 15 eV were visible in the developed resist. The limit at 15 eV is related to the operation of the STM and does not represent an exposure threshold energy for the resist.

Fabrication of a planar grating spectrograph by deep-etch lithography with synchrotron radiation

Abstract: A three-layer resist system has been developed which can be used for light guiding. By structuring these layers with deep-etch X-ray lithography, high-precision multimode lightguide components with a relatively low attenuation can be produced. As a first example, a planar grating spectrograph with a self-focusing reflection grating has been fabricated together with fibre-fixing grooves. The spectro-graph shows an excellent dispersion of the light as well as a low cross-talk between the channels.

Optimization of optical properties of resist processes

Abstract: Thin film interference plays a dominant role in CD control of single layer photoresist processes, causing large changes in the effective exposure dose due to a tiny change in optical phase. Such interference effects are evident in the sinusoidal undulations of a plot of dose to clear versus resist thickness, the 'swing curve'. To quantify the interference swing, we define the swing ratio S as the ratio of the peak to valley change to the average value in the swing curve. S is a fundamental figure of merit for photoresist processes, since linewidth variations with small changes in resist thickness are proportional to S. A simple optical model of photoresist (as a Fabry-Perot etalon) leads to the following analytical expression for the swing ratio S: S approximately equals 4(root)R1R2 e-(alpha D) where R1 is the reflectivity of the resist/air interface, R2 is the reflectivity of the resist/substrate interface, and (alpha) is the resist absorption coefficient. Efforts to improve process control have lead to the invention of many cleaver resist processes including Top Surface Imaging (TSI), Anti-Reflection Coats (ARC), dyed resists, etc. Eq. 1 allows a classification of these processes according to which factor is modified. For example, TSI and dyed resist processed reduce S by increasing (alpha) . ARC processes reduce S as the square root of substrate reflectivity under the resist R2. Fundamental limits of the performance of thin absorbing ARC layers will be described. A novel approach, termed the Top Anti-Reflector (TAR) process, reduces the reflection at the top of the resist R1 and can be shown to dramatically improve process control over varying thicknesses of resist and thin film layers. The effects of multiple wavelength exposure and oblique rays from high NA optics are also briefly examined.

Phase-shifting and other challenges in optical mask technology

Abstract: Optical lithography has benefitted from progresses in wavelength reduction, lenses, resist systems, alignment, focussing, table accuracy, and insute metrology. As a result, the minimum feature size of integrated circuits has been reduced through many generations from 2 micrometers to 0.5 micrometers in manufacturing. There are many opportunities in improving the mask to help continue the progress. The image contrast can be restored by reducing stray light with mask anti-reflection coating at the absorber-air interface. Pre-distorting the mask against the distortion of the imaging lens can drastically improve the overlay performance. Adjusting the gray level or the feature size individually according to the pattern proximity environment can create a larger common exposure-defocus window for different feature shapes. Introducing phase shifts in the mask can simultaneously improve resolution and depth of focus, with the potential of a two-generation improvement with any given projection imaging equipment, provided the overlay capability is upgraded accordingly. In addition to describing and comparing these opportunities, the phase-shifting technology is given a special focus on the working principle, the different approaches to phase shifting, their imaging characteristics in terms of exposure-defocus diagrams, a systems view, and the scope of its development.

Reactive ion etching buffer mask

Abstract: An improved mask and method of forming a deep and uniform width trench in a substrate and the resulting structure is disclosed A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask The silicon dioxide is patterned in the form of the trench to be formed in the substrate The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material Thus, only those ions which are directed essentially normal to the underlying substrate perform the trench etching This allows the trench to have essentially straight side walls and to be of essentially uniform width

Self-aligned cylindrical stacked capacitor DRAM cell

Abstract: A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. An etch mask is now formed on the second polysilicon layer and the second polysilicon layer is anisotropically etching to form a shell-shaped second polysilicaon layer. A capacitor dielectric layer is formed over the shell-shaped second polysilicon layer. A third polysilicon layer is deposited and patterned as the top storage node electrode to complete the stacked capacitors. The etch mask can either be formed in part by a lateral etching of a resist mask or is formed in part by use of a sidewall spacer structure and mask. The first insulator layer is patterned to expose the source/drain structures to electrical contact either before or after the deposition of the second polysilicon layer.

Pattern Transfer Characteristics of Transparent Phase Shifting Mask

Abstract: Phase shifting technologies achieve significant improvement in both resolution and depth of focus (DOF). We have proposed a "transparent-type" phase shifting mask which has a simple structure (no Cr layer) that considerably improves the resolution limit of optical lithography.1) In this paper, we describe in detail pattern transfer characteristics of the transparent phase shifting mask with i-line steppers. The effects of numerical aperture (NA) and coherence factor (σ) on the resolution capability and DOF were investigated using simulations and experiments. Patterns are printed using i-line steppers with a numerical aperture (NA) of 0.45 and 0.65. A pattern of 0.23 µm lines and spaces is resolved with a 0.45 NA i-line stepper. DOF for 0.25-µm features is found to be in the 1.5-µm range. Well-resolved 0.18-µm lines and spaces are obtained with a 0.65-NA i-line stepper. Transparent phase shifting mask technologies extend the resolution limit of i-line lithography to the resist features below 0.2 µm.

Method of forming t-gate structure on microelectronic device substrate

Abstract: A T-gate structure (28a) is fabricated on a microelectronic device substrate (10) using a trilevel resist system in combination with a two-step reactive ion etching (RIE) technique utilizing an oxygen plasma. The trilevel resist consists of a planarizing resist layer (12), masking layer (14) and imaging resist layer (16), which are formed on the surface (10a) of the substrate (10). A focused ion beam (18) is then used to expose the uppermost imaging layer (16) with an image having a width equal to the desired gate length of the T-gate structure (28a). The imaged area is developed and etched to form an opening (14a,16a) of the same width through the imaging layer (16) and also through the masking layer (14). In the first oxygen RIE step, the planarizing resist layer (12) is etched isotropically through the opening (14a,16a), partially down to the substrate surface (10a) to form a cavity (12a) having a width which is larger than the width of the opening (14a,16a). The second oxygen RIE step is used to etch the planarizing resist layer (12) through the opening (14a,16a) completely down to the substrate surface (10a) to form a notch (12a) underneath the cavity (12a) having a width substantially equal to the width of the opening (14a,16a) and thereby the gate length of the T-gate structure (28a). The imaging layer (16) and masking layer (14) are removed, and metal (28) is evaporated onto the substrate (10) to fill the cavity (12a) and notch (12b) and thereby form the T-gate structure (28a). The first resist layer (12) and overlying metal (28) are lifted off, leaving the T-gate structure (28a) on the surface (10a) of the substrate (10).

Tapered opening sidewall with multi-step etching process

Abstract: A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer. The remaining thickness of the multilayer insulating layer is anisotropically etched through to the semiconductor substrate to form the desirable tapered opening with a metal step coverage improvement over the state of the art between about 20 to 60%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in the contact hole to the metal thickness on the horizontal area. The resist layer mask is removed.

Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system)

Abstract: A three-dimensional topographical simulator PEACE (photo and electron beam lithography analyzing computer engineering system) is discussed One of the difficulties in resist topographical simulation exists due to the three-dimensional resist development algorithm An algorithm based on the cell removal model provides accurate and stable results for the three-dimensional resist development process The program has been adapted to a supercomputer for quick computation The simulator can successfully perform the three-dimensional development in an absolutely stable manner, and good agreement can be obtained with experiments for both photo and electron beam lithography >

Process for manufacturing printed circuit employing selective provision of solderable coating

Abstract: The areas of a printed circuit where electrical components are to be solder connected, such as through-holes (H), surrounding pads (P) and surface mount areas (SMT), are selectively provided with a metal coating (22) (e.g., tin-lead) which preserves and promotes solderability thereat, by a process in which a photoimageable electrophoretically deposited organic resin (20) is used to provide, on an already patterned surface, an additional resist pattern which selectively exposes areas on which the solderable metal coating is to be provided and in which the resist serves also as an etch resist for metal areas over which it is arranged.