Showing papers on "Resist published in 2005"

Vapor-phase self-assembled monolayer for improved mold release in nanoimprint lithography

Abstract: Resist adhesion to the mold is one of the challenges for nanoimprint lithography. The main approach to overcoming it is to apply a self-assembled monolayer of an organosilane release agent to the mold surface, either in the solution phase or vapor phase. We compared the atomic force microscopy, ellipsometry, reflection−absorption infrared spectroscopy, and contact angle results collected from substrates treated by two different application processes and found that the vapor-phase process was superior. The vapor-treated substrates had fewer aggregates of the silane molecules on the surface, because the lower density of the agent in the vapor phase was not conducive to aggregation formation, and received a superior coating of the releasing agent, because the vapor was more effective than the solution in penetrating into the nanoscale gaps of the mold. A pattern transfer of 20 parallel nanowires with a line width of 40 nm at 100 nm pitch-size was performed faithfully with the vapor-treated mold without any r...

Resist blur and line edge roughness (Invited Paper)

Abstract: A straightforward analytic model of resist line edge roughness is presented which predicts all the known scaling laws as well as the shape of the experimentally seen frequency content or power spectrum of the roughness. The model implies there are strong basic limitations to achieving, simultaneously, low roughness, low dose and high resolution in any standard chemically amplified resist process. A simple model of how roughness maps to device performance is also presented.

Hybrid planar and FinFET CMOS devices

Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

Impact of polymer film thickness and cavity size on polymer flow during embossing: toward process design rules for nanoimprint lithography

Abstract: This paper presents continuum simulations of polymer flow during nanoimprint lithography (NIL). The simulations capture the underlying physics of polymer flow from the nanometer to millimeter length scale and examine geometry and thermophysical process quantities affecting cavity filling. Variations in embossing tool geometry and polymer film thickness during viscous flow distinguish different flow driving mechanisms. Three parameters can predict polymer deformation mode: cavity width to polymer thickness ratio, polymer supply ratio and capillary number. The ratio of cavity width to initial polymer film thickness determines vertically or laterally dominant deformation. The ratio of indenter width to residual film thickness measures polymer supply beneath the indenter which determines Stokes or squeeze flow. The local geometry ratios can predict a fill time based on laminar flow between plates, Stokes flow, or squeeze flow. A characteristic NIL capillary number based on geometry-dependent fill time distinguishes between capillary- or viscous-driven flows. The three parameters predict filling modes observed in published studies of NIL deformation over nanometer to millimeter length scales. The work seeks to establish process design rules for NIL and to provide tools for the rational design of NIL master templates, resist polymers and process parameters.

Microfluidic channel fabrication in dry film resist for production and prototyping of hybrid chips

Abstract: Microfluidic networks are patterned in a dry film resist (Ordyl SY300/550) that is sandwiched in between two substrates. The technique enables fabrication of complex biochips with active elements both in the bottom and the top substrate (hybrid chips). The resist can be double bonded at relatively low temperatures without the use of extra adhesives. A postbake transfers the resist into a rigid structure. The resist is qualified in terms of resolution, biocompatibility and fluidic sealing. Fabrication in both a fully equipped cleanroom setting as well as a minimally equipped laboratory is described. The technique is applied for dielectrophoresis-based cell separation systems and a fuel cell reaction chamber with micropillars. The dry film resist can be considered a cheap and fast alternative to SU-8.

Method of making a microelectronic and/or optoelectronic circuitry sheet

Abstract: A circuitry sheet (322) comprising an electronic device layer stack (304) containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method (200) that includes the steps of forming the device layer stack on a temporary substrate (300), removing material from both sides of the device layer stack, and then attaching a permanent substrate (348) to the device layer stack. The method uses one or more resist layers (600) that may be activated simultaneously and independently to impart distinct circuit pattern images (603, 608, 612) into each of a plurality of image levels (612, 616, 620) within each resist layer, thereby obviating repetitive sequential exposure, registration and alignment steps.

6 nm half-pitch lines and 0.04 νm 2 static random access memory patterns by nanoimprint lithography

Abstract: A key issue in nanoimprint lithography (NIL) is determining the ultimate pitch resolution achievable for various pattern shapes and their critical dimensional control. To this end, we demonstrated the fabrication of 6 nm half-pitch gratings and 0.04 µm2 cell area SRAM metal interconnects with 20 nm line half-pitch in resist by NIL. The mould for the 6 nm half-pitch grating was fabricated by cleaving a GaAs /Al0.7Ga0.3As superlattice grown on GaAs with molecular beam epitaxy, and selectively etching away the Al0.7Ga0.3As layers in dilute hydrofluoric acid. The mould for the 0.04 µm2 SRAM metal interconnects was fabricated in silicon dioxide using 35 kV electron beam lithography with polystyrene as a negative resist and a reactive ion etch with the resist as mask. Imprints from both moulds showed excellent fidelity and critical dimension control.

Photolithography scheme using a silicon containing resist

Abstract: A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.

Method of manufacturing a semiconductor device

Abstract: By using a high-accuracy mask capable of being manufactured through a simplified step, a semiconductor device manufacturing method of forming a desired pattern over a wafer is provided. A relatively narrow groove pattern and a groove pattern wider than the narrow groove pattern are formed, and a shade film made of, for example, a resist film is formed in the relatively wide groove pattern. As a concrete method of manufacturing a mask, after applying a resist film onto the quartz glass substrate, exposure and developing processings are performed, whereby the resist film is patterned. The patterned resist film is used as a mask to form the groove patterns in the quartz glass substrate (dry etching). Subsequently, after removing the patterned resist film, a new resist film is applied. Then, patterning is performed to form the shade film only in the groove pattern.

Effect of low numerical-aperture femtosecond two-photon absorption on (SU-8) resist for ultrahigh-aspect-ratio microstereolithography

Abstract: We report the quantitative characterization and analysis on the solidification of SU-8, a chemically amplified near-ultraviolet ultrathick resist, based on two-photon-absorbed (TPA) near-infrared photopolymerization. The resolution of TPA photopolymerized SU-8 voxels and lines is studied as a function of laser-pulse energy, single-shot exposure time, and scanning speed. Two-photon microstereolithography using SU-8 as the matrix material was verified by the fabrication of SU-8 photoplastic structures with subdiffraction-limit resolution. We show that the nonlinear velocity dependence of TPA photopolymerization can be used as the shutter mechanism for disruptive three-dimensional (3D) lithography. This mechanism, when combined with low numerical-aperture optics is exploited for the rapid 3D microfabrication of ultrahigh-aspect-ratio (up to 50:1) photoplastic pillars, planes, and cage structures.

Resist underlayer film material and pattern forming method

Abstract: PROBLEM TO BE SOLVED: To provide a resist underlayer film material which is a resist underlayer film material for a multilayered resist process for, for example, a resist upperlayer film containing silicon, and more particularly for a two-layer resist process, functions as an excellent antireflection film to exposure of a short wavelength in particular, i.e., has the transparency higher than that of polyhydroxy strene, cresol novolak, naphthol novolak, etc., has an optimum (n) value (refractive index), and (k) value (extinction coefficient) and has excellent etching resistance in substrate working, and a method for forming the pattern to a substrate by lithography using the same. SOLUTION: The resist underlayer film material for the multilayered resist films used for lithography contains at least the polymer expressed by general formula (1). COPYRIGHT: (C)2004,JPO&NCIPI

One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography

Abstract: We have developed a process to fabricate a cross-bar structure using UV-curable nanoimprint lithography with a UV-curable double-layer spin-on resist, metal lift off and Langmuir–Blodgett film deposition. This process allowed us to produce 1-kbit cross-bar memory circuits at 30-nm half-pitch on both top and bottom electrodes. Read, write, erase and cross talking were also investigated.

Photolithographic route to the fabrication of micro/nanowires of III-V semiconductors

Abstract: Nano/microwires of semiconducting materials (e.g., GaAs and InP) with triangular cross-sections can be fabricated by "top-down" approaches that combine lithography of high-quality bulk wafers (using either traditional photolithography or phase-shift optical lithography) with anisotropic chemical etching. This method gives good control over the lateral dimensions, lengths, and morphologies of free-standing wires. The behaviors of many different resist layers and etching chemistries are presented. It is shown how wire arrays with highly ordered alignments can be transfer printed onto plastic substrates. This "top-down" approach provides a simple, effective, and versatile way of generating high-quality single-crystalline wires of various compound semiconductors. The resultant wires and wire arrays have potential applications in electronics, optics, optoelectronics, and sensing.

Sub-20 nm short channel carbon nanotube transistors

Abstract: Carbon nanotube field-effect transistors with sub-20 nm long channels and on/off current ratios of >10(6) are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 to 1.1 nm grown from structured catalytic islands using chemical vapor deposition at 700 degrees C form the channels. Electron beam lithography and a combination of HSQ, calix[6]arene, and PMMA e-beam resists were used to structure the short channels and source and drain regions. The nanotube transistors display on-currents in excess of 15 microA for drain-source biases of only 0.4 V.

Methods of removing resist from substrates in resist stripping chambers

Abstract: Methods for stripping resist from a semiconductor substrate in a resist stripping chamber are provided. The methods include producing a remote plasma containing reactive species and cooling the reactive species inside the chamber prior to removing the resist with the reactive species. The reactive species can be cooled by being passed through a thermally-conductive gas distribution member. By cooling the reactive species, damage to a low-k dielectric material on the substrate can be avoided.

Manufacture method for micro structure

Abstract: A micro structure manufacture method includes the steps of: (a) preparing an etching object having an etching target film, provided with a lower hard mask layer and an upper hard mask layer stacked on the etching target film; (b) forming a resist pattern above the etching object; (c) etching the upper hard mask film by using the resist pattern as an etching mask to form an upper hard mask; (d) after the step (c), removing the resist pattern; (e) after the step (d), thinning the upper hard mask by etching; (f) etching the lower hard mask film by using the thinned upper hard mask as an etching mask to form a lower hard mask; and (g) etching the etching target film by using the upper hard mask and the lower hard mask as an etching mask, wherein the upper hard mask film is capable of being more easily etched, using the resist pattern as a mask, than the lower hard mask film. The micro structure manufacture method can etch a fine pattern with good yield.

A numerical and experimental study on gap compensation and wavelength selection in UV-lithography of ultra-high aspect ratio SU-8 microstructures

Abstract: This paper presents a study on UV-lithography of thick SU-8 resist using air gap compensation and optimal wavelength selection for ultra-high aspect ratio microstructures. Both numerical simulations and experiments were conducted to study effects of different lithography conditions: broadband light source with and without air gap compensation, filtered light source with glycerol liquid, and filtered light source with Cargille refractive index matching liquid. A thick PMMA sheet was used as an optical filter to eliminate most of the i-line components of a broadband light source. Using the filtered light source and gap compensation with the Cargille refractive index liquid perfectly matching that of SU-8, patterns with feature sizes of 6 μm thick, 1150 μm tall (aspect ratio of more than 190:1) and high quality sidewalls were obtained. Microstructures with height up to 2 mm and good sidewall quality were also obtained and presented. The study also proved that Cargille refractive index matching liquid is compatible with UV-lithography of SU-8 and may be used as an effective air gap compensation solution.

Potential Cause of Inhomogeneous Acid Distribution in Chemically Amplified Resists for Post Optical Lithography

Abstract: In chemically amplified resists for ionizing radiation such as an electron beam and EUV, protons of acids are mainly generated by the deprotonation of base polymers. Therefore, the acid generation efficiency depends highly on polymer structure. In recent resist formulas, partially protected poly(4-hydroxystyrene) has often been used as a base polymer. In this work, the effects of protecting groups on acid generation were investigated. We found differences in acid generation efficiency caused by protecting groups. These differences are likely to affect acid distribution.

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Abstract: Using 193nm lithography at NA=0.75, the minimum pitch that can be obtained in a single exposure is 160nm for dark field structures that are used in single damascene interconnect processing. In order to evaluate the critical electrical parameters for the smaller technologies, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm. This corresponds to k1-factors of 0.27 to 0.19 for dense trenches. The designs have been split up into two layers at more relaxed pitch (twice the final pitch). The first step consists in patterning a small semi-isolated trench at this more relaxed pitch. Because of the limited resist resolution for semi-isolated trenches, shrink techniques such as resist reflow or RELACS are needed. After etching this first layer into a low-k material or metal hard mask, planarization of the topography is critical before performing the second exposure. The second exposure is then identical to the first one, but overlay to the first layer is extremely critical in order to get a reasonable process window. In this paper, we illustrate the feasibility of the double patterning technique for early sub-65nm-node evaluation of low-k materials. The resolution and processing limits will be shown for single layer resist processing with RELACS shrink for 193nm lithography at NA=0.75. The planarization for the second photo is done using organic BARC. We will also quantify the overlay requirements to measured and introduced overlay errors.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To enable a resistor composed of a thin metallic film to obtain a stable resistance value by preventing the oxidation of the surface of the metallic film even when oxygen ashing is performed on a resist SOLUTION: A method of manufacturing a semiconductor device includes a step (a) of forming a thin metallic film 5 on a base insulating film 3; a step (b) of laminating a silicon nitride film 7 and a silicon oxide film 9 upon the film 5 in this order; and a step (c) of removing a photoresist pattern 11 by performing ashing by using oxygen plasma, after the pattern 11 is formed on the silicon oxide film 9 for demarcating a resistor forming area and a silicon oxide film pattern 9a is formed by selectively removing the silicon oxide film 9 by using the photoresist pattern 11 as a mask The method also includes a step (d) of forming a silicon nitride film pattern 7a by selectively removing the silicon nitride film 7 and thin metallic film 5 by using the silicon oxide film pattern 9a as a mask and forming a thin metallic film pattern 5a which becomes the resistor, and a step (e) of forming a oxidation preventing second silicon nitride film 13 on the side face of the thin metallic film pattern 5a COPYRIGHT: (C)2005,JPO&NCIPI

Method for forming a finely patterned resist

Abstract: A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.

Room-Temperature, Low-Pressure Nanoimprinting Based on Cationic Photopolymerization of Novel Epoxysilicone Monomers.

Abstract: A new UV-curable liquid resist based on cationic polymerization of silicone epoxies has been developed for UV-assisted nanoimprint lithography. Uniform films with thicknesses ranging from below 50 nm to over 1 μm can be easily spin-coated using a suitable undercoating layer on a substrate. Patterns with feature sizes ranging from tens of micrometers to 20 nm are imprinted at room temperature with a pressure of less than 0.1 MPa.

Method for manufacturing semiconductor device

Abstract: Provided is a method of manufacturing a semiconductor device capable avoiding occurrence of resist residue on a gate opening portion when forming the gate opening portion finely for injecting an impurity to form an asymmetric transistor during patterning of a gate electrode The method of manufacturing the semiconductor device, in a case of manufacturing a DRAM (Dynamic Random Access Memory) with a memory cell transistor made up of the asymmetric transistor, performs separately a first gate electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a capacitive element via a capacitive contact connect, and a gate second electrode patterning process for forming a high concentration N-type diffusion region to be electrically connected to a bit line via a bit contact

Thin film transistor device and method of manufacturing the same

Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

Shaping a phase change layer in a phase change memory cell

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of Damascene structure capable of decreasing a pitch at which interconnect lines are arranged without causing a short circuit to the adjacent interconnect lines or adjacent vias, and to provide its manufacturing method. SOLUTION: A first interconnect line 14, a via 15 interconnecting first and second wiring layer, and a second interconnect line 16 are formed on a semiconductor substrate 1, then a first cover insulating film 8 processed so as to be narrower than a space between the interconnect lines is formed on the second interconnect line layer 16, and a second cover insulating film 9 is deposited thereon and then etched back to form a nearly flat hard mask composed of the first cover insulating film 8 and the second cover insulating film 9. The second interlayer insulating film 11 and the first cover insulating film 8 are subjected to etching, using a resist pattern provided on the second interlayer insulating film 11 on the above flat hard mask, whereby the underlying insulating film is removed with the hard mask formed of the second cover insulating film 9 to form a second via hole 23. By this setup, embedding failures of the interlayer insulating films are prevented from occurring, and the pitch of the second interconnect line 16 is reduced. COPYRIGHT: (C)2004,JPO&NCIPI

Effect of plasma interactions with low-κ films as a function of porosity, plasma chemistry, and temperature

Abstract: Integration of new low-κ interlayer dielectrics (ILD) with current damascene schemes is a continuing issue in the microelectronics industry. During integration of the ILD, processing steps such as plasma etching, resist strip, and chemical-mechanical planarization are known to chemically alter a layer of the dielectric. Here, porous organosilicate glass (OSG) ILD films, which—according to the 2004 edition of the International Technology Roadmap for Semiconductors—are projected for use in the 65 and 45 nm nodes, are investigated. spectroscopic ellipsometry, x-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy are used to characterize the modified layer of the ILD after exposure to O2 or H2 resist strip plasmas. The effects of the two types of plasma etch chemistries on the formation of the modified layer were found to differ significantly. These effects include both the degree of modification (i.e., chemical composition) and depth of the modified layer. A key difference between the...

Facile Scheme for Fabricating Solid-State Nanostructures Using E-Beam Lithography and Solution Precursors

Abstract: We demonstrate a facile approach for site-specific fabrication of organic, inorganic, and hybrid solid-state nanostructures through a novel combination of electron-beam lithography (eBL) and spin coating of liquid and sol-gel precursors, termed soft eBL. By using eBL patterned resists as masks in combination with a low cost process such as spin coating, directed growth of nanostructures with controlled dimensions is achieved without the need for the costly and difficult process step of etching ceramics. The highly versatile nature of the scheme is highlighted through the fabrication of nanostructures of a variety of materials such as ferroelectric, optoelectronic, and conducting polymeric materials at different length scales and spatial densities on a multitude of substrates.