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Showing papers on "Resist published in 2007"


Journal ArticleDOI
TL;DR: In this paper, the basic principles of nano-printing are discussed, with an emphasis on the requirements on materials for the imprinting mold, surface properties, and resist materials for successful and reliable nanostructure replication.
Abstract: Nanoimprint lithography (NIL) is a nonconventional lithographic technique for high-throughput patterning of polymer nanostructures at great precision and at low costs. Unlike traditional lithographic approaches, which achieve pattern definition through the use of photons or electrons to modify the chemical and physical properties of the resist, NIL relies on direct mechanical deformation of the resist material and can therefore achieve resolutions beyond the limitations set by light diffraction or beam scattering that are encountered in conventional techniques. This Review covers the basic principles of nanoimprinting, with an emphasis on the requirements on materials for the imprinting mold, surface properties, and resist materials for successful and reliable nanostructure replication.

1,644 citations


Book
01 Jan 2007
TL;DR: In this article, the authors present an approach for image formation in resist using the Dirac Delta Function (DDF) and a normalized image log-slope, which is used to detect critical dimension variations.
Abstract: Preface. 1. Introduction to Semiconductor Lithography. 1.1 Basics of IC Fabrication. 1.2 Moore's Law and the Semiconductor Industry. 1.3 Lithography Processing. Problems. 2. Aerial Image Formation - The Basics. 2.1 Mathematical Description of Light. 2.2 Basic Imaging Theory. 2.3 Partial Coherence. 2.4 Some Imaging Examples. Problems. 3. Aerial Image Formation - The Details. 3.1 Aberrations. 3.2 Pupil Filters and Lens Apodization. 3.3 Flare. 3.4 Defocus. 3.5 Imaging with Scanners Versus Steppers. 3.6 Vector Nature of Light. 3.7 Immersion Lithography. 3.8 Image Quality. Problems. 4. Imaging in Resist: Standing Waves and Swing Curves. 4.1 Standing Waves. 4.2 Swing Curves. 4.3 Bottom Antirefl ection Coatings. 4.4 Top Antirefl ection Coatings. 4.5 Contrast Enhancement Layer. 4.6 Impact of the Phase of the Substrate Refl ectance. 4.7 Imaging in Resist. 4.8 Defi ning Intensity. Problems. 5. Conventional Resists: Exposure and Bake Chemistry. 5.1 Exposure. 5.2 Post-Apply Bake. 5.3 Post-exposure Bake Diffusion. 5.4 Detailed Bake Temperature Behavior. 5.5 Measuring the ABC Parameters. Problems. 6. Chemically Amplifi ed Resists: Exposure and Bake Chemistry. 6.1 Exposure Reaction. 6.2 Chemical Amplifi cation. 6.3 Measuring Chemically Amplifi ed Resist Parameters. 6.4 Stochastic Modeling of Resist Chemistry. Problems. 7. Photoresist Development. 7.1 Kinetics of Development. 7.2 The Development Contrast. 7.3 The Development Path. 7.4 Measuring Development Rates. Problems. 8. Lithographic Control in Semiconductor Manufacturing. 8.1 Defi ning Lithographic Quality. 8.2 Critical Dimension Control. 8.3 How to Characterize Critical Dimension Variations. 8.4 Overlay Control. 8.5 The Process Window. 8.6 H-V Bias. 8.7 Mask Error Enhancement Factor (MEEF). 8.8 Line-End Shortening. 8.9 Critical Shape and Edge Placement Errors. 8.10 Pattern Collapse. Problems. 9. Gradient-Based Lithographic Optimization: Using the Normalized Image Log-Slope. 9.1 Lithography as Information Transfer. 9.2 Aerial Image. 9.3 Image in Resist. 9.4 Exposure. 9.5 Post-exposure Bake. 9.6 Develop. 9.7 Resist Profi le Formation. 9.8 Line Edge Roughness. 9.9 Summary. Problems. 10. Resolution Enhancement Technologies. 10.1 Resolution. 10.2 Optical Proximity Correction (OPC). 10.3 Off-Axis Illumination (OAI). 10.4 Phase-Shifting Masks (PSM). 10.5 Natural Resolutions. Problems. Appendix A. Glossary of Microlithographic Terms. Appendix B. Curl, Divergence, Gradient, Laplacian. Appendix C. The Dirac Delta Function. Index.

514 citations


Journal ArticleDOI
TL;DR: In this paper, a broad range of topics, including history, tools, source, metrology, condenser and projection optics, resists, and masks, are thoroughly reviewed over a broad variety of topics.
Abstract: Extreme ultraviolet lithography (EUVL) was thoroughly reviewed over a broad range of topics, including history, tools, source, metrology, condenser and projection optics, resists, and masks. Since 1988, many studies on EUVL have been conducted in North America, Europe, and Japan, through state sponsored programs and industrial consortiums. To date, no “show stopper” has been identified, but challenges are present in almost all aspects of EUVL technology. Commercial alpha lithography step-and-scan tools are installed with full-field capability; however, EUVL power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 180W IF power, current tools can supply only approximately 55–62W. EUV IF power has been improved gradually from xenon- to tin-discharge-produced plasma or laser-produced plasma. EUVL resist has improved significantly in the last few years, with 25nm 1:1 line/space resolution being produced with approximately 2.7nm (3σ) line edge roughness. A...

363 citations


Patent
29 Jun 2007
TL;DR: In this article, the authors proposed a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

323 citations


Journal ArticleDOI
TL;DR: Different SU‐8‐based techniques have led to new low‐temperature processes suitable for the fabrication of a wide range of objects, from the single component to the complete lab‐on‐chip.
Abstract: Since its introduction in the nineties, the negative resist SU-8 has been increasingly used in micro- and nanotechnologies. SU-8 has made the fabrication of high-aspect ratio structures accessible to labs with no high-end facilities such as X-ray lithography systems or deep reactive ion etching systems. These low-cost techniques have been applied not only in the fabrication of metallic parts or molds, but also in numerous other micromachining processes. Its ease of use has made SU-8 to be used in many applications, even when high-aspect ratios are not required. Beyond these pattern transfer applications, SU-8 has been used directly as a structural material for microelectromechanical systems and microfluidics due to its properties such as its excellent chemical resistance or the low Young modulus. In contrast to conventional resists, which are used temporally, SU-8 has been used as a permanent building material to fabricate microcomponents such as cantilevers, membranes, and microchannels. SU-8-based techniques have led to new low-temperature processes suitable for the fabrication of a wide range of objects, from the single component to the complete lab-on-chip. First, this article aims to review the different techniques and provides guidelines to the use of SU-8 as a structural material. Second, practical examples from our respective labs are presented.

243 citations


Patent
21 Dec 2007
TL;DR: In this paper, a pattern-forming method was proposed, in which a substrate is coated with a positive resist composition of which solubility increases and decreases upon irradiation with actinic rays or radiation, so as to form a resist film.
Abstract: A pattern forming method, including: (A) coating a substrate with a positive resist composition of which solubility in a positive developer increases and solubility in a negative developer decreases upon irradiation with actinic rays or radiation, so as to form a resist film; (B) exposing the resist film; and (D) developing the resist film with a negative developer; a positive resist composition for multiple development used in the method; a developer for use in the method; and a rinsing solution for negative development used in the method.

225 citations


Patent
19 Feb 2007
TL;DR: In this article, a 1-20C mono-to- tetra-valent carboxylate of metal selected from sodium, magnesium, chromium, manganese, iron, cobalt, nickel, copper, zinc, silver, tin, antimony, cesium, zirconium and hafnium, or a complex of the metal and β-diketones, was obtained by compounding a polymeric compound prepared by polymerization of a repeating unit of (meth)acrylate, styrene carboxylic acid
Abstract: PROBLEM TO BE SOLVED: To provide a resist material that has high resolution and also high sensitivity, achieves a favorable pattern profile after exposure to light and causes small line edge roughness,a chemically amplified positive resist material that has electrically conductive features and prevents charge-up during drawing, and a pattern forming method using the material.SOLUTION: The resist material is obtained by compounding a 1-20C mono- to tetra-valent carboxylate of metal selected from sodium, magnesium, chromium, manganese, iron, cobalt, nickel, copper, zinc, silver, cadmium, indium, tin, antimony, cesium, zirconium and hafnium, or a complex of the metal and β-diketones, into a resist material containing an acid generator and a polymeric compound prepared by (co)polymerization of a repeating unit of (meth)acrylate, styrene carboxylic acid or vinylnaphthalene carboxylic acid substituted with an acid-labile group and/or a repeating unit having a phenolic hydroxyl group substituted with an acid-labile group. The resist material shows significantly high contrast in an alkali dissolution rate before and after exposure, has high sensitivity and high resolution, gives a favorable pattern profile, and moreover suppresses an acid diffusion rate and causes small line edge roughness.

213 citations


Journal ArticleDOI
TL;DR: In this article, the authors used a mixture of salt and alkali to significantly increase the contrast of hydrogen silsesquioxane (HSQ) for negative-tone electron-beam resist.
Abstract: When used as a negative-tone electron-beam resist, hydrogen silsesquioxane (HSQ) is typically developed in an aqueous alkali solution such as tetramethyl ammonium hydroxide. This development process results in low contrast. In this work, the authors instead used a mixture of salt and alkali to significantly increase the contrast of HSQ. Contrast values as high as 10 in a 115‐nm-thick resist were achieved by developing HSQ in an aqueous mixture of NaOH alkali and NaCl salt. Remarkably, this salty developer resulted in contrast enhancement without significant decrease in resist sensitivity. The improved contrast of HSQ enabled the fabrication of 7nm half-pitch nested-“L” structures in a 35‐nm-thick resist with minimal loss in thickness using a 30kV electron-beam acceleration voltage. They noticed a strong dependence of contrast enhancement on the concentration and type of cations and anions in the aqueous developer solution.

208 citations


Patent
Nakai Satoshi1
08 Feb 2007
TL;DR: In this article, a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate, wet-etching the first gate-insulating film of the second active region through a first resist opening portion of a first-resistance pattern, forming a second gate-inhibiting film in the second-active region, forming on the silicon substrate a second-residual pattern having a second resist portion larger than the first-Residual opening portion, and forming a third-gate insulating film
Abstract: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region

202 citations


Proceedings ArticleDOI
TL;DR: A novel double patterning method that does not include transfer etch in between the lithography steps is examined and an assessment will be made whether the proposed technique has the potential to be used in production.
Abstract: Double patterning has become one of the candidates to bring us to the next node of the ITRS-roadmap. As an alternative to immersion lithography with higher index fluids and EUV lithography which both require considerable changes in infrastructure, double patterning makes use of the existing infrastructure. Because of this, double patterning has gained considerable attention during the past few years. It has become a serious candidate to reach the 45 nm node and even the 32 nm node. Most of the currently known double patterning techniques have relatively complex process flows, which may prevent them from being used in production. One of the complicating factors is the use of an etch step in between the two lithography steps. This etch step is necessary to transfer the pattern of the first resist layer into an underlying hard mask before a second exposure can be done. Another complicating element, arising in several known double patterning techniques, is the translation of overlay error in CD-error. This translation occurs when a feature is printed in two exposures, i.e. not features but the spaces between them are patterned, patterning the left and right edge of a feature in different exposures. In this paper, we examine and evaluate a novel double patterning method that does not include transfer etch in between the lithography steps. This method would simplify the double patterning process. Furthermore, each feature is patterned completely in one exposure, for which CD-value is not affected by overlay error. This paper discusses the feasibility of the new double patterning method and compares it to conventional double patterning schemes. Furthermore, an assessment will be made whether the proposed technique has the potential to be used in production.

192 citations


Proceedings ArticleDOI
TL;DR: A novel double exposure inverse lithography technique (ILT) is proposed to split the pattern, based on the earlier proposed single exposure ILT framework, and it demonstrates that double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography.
Abstract: Multiple paths exists to provide lithography solutions pursuant to Moore's Law for next 3-5 generations of technology, yet each of those paths inevitably leads to solutions eventually requiring patterning at k1 < 0.30 and below. In this article, we explore double exposure single development lithography for k1 ≥ 0.25 (using conventional resist) and k1 < 0.25 (using new out-of-sight out-of-mind materials). For the case of k1 ≥ 0.25, we propose a novel double exposure inverse lithography technique (ILT) to split the pattern. Our algorithm is based on our earlier proposed single exposure ILT framework, and works by decomposing the aerial image (instead of the target pattern) into two parts. It also resolves the phase conflicts automatically as part of the decomposition, and the combined aerial image obtained using the estimated masks has a superior contrast. For the case of k1 < 0.25, we focus on analyzing the use of various dual patterning techniques enabled by the use of hypothetic materials with properties that allow for the violation of the linear superposition of intensities from the two exposures. We investigate the possible use of two materials: contrast enhancement layer (CEL) and two-photon absorption resists. We propose a mathematical model for CEL, define its characteristic properties, and derive fundamental bounds on the improvement in image log-slope. Simulation results demonstrate that double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography. We also combine ILT, CEL, and DEL to synthesize 2-D patterns with k1 = 0.185. Finally, we discuss the viability of two-photon absorption resists for double exposure lithography.

Proceedings ArticleDOI
TL;DR: In this article, double patterning of k 1-effective = 0.25 with improved process window using a negative resist was demonstrated, where two etch transfer steps were incorporated into the hard mask material and frequency doubled patterns could be obtained.
Abstract: Double exposure is one of the promising methods for extending lithographic patterning into the low k 1 regime. In this paper, we demonstrate double patterning of k 1-effective =0.25 with improved process window using a negative resist. Negative resist (TOK N- series) in combination with a bright field mask is proven to provide a large process window in generatin g 1:3 = trench:line resist features. By incorporating two etch transfer steps into the hard mask material, frequency doubled patterns could be obtained. Keywords : Double exposure, double patterning, 193 nm, negative tone 1. INTRODUCTION Resolution is expressed by P/2 = k 1 O /NA, where P/2 is the minimum half pitch, k 1 is a process factor, O is the wavelength of the exposure light, and NA is the numerical aperture of the projection optics. In order to extend the resolution limit, many resolution enhancement techniques have been developed. Among those many potential techniques, double exposure methods are being considered to be promising in 193 nm lithography (Fig. 1). Recently, several double exposure techniques have been reported such as UV resist-modification [1], double dipole [2], spacer technique [3], and double patterning [4]. Among those, double patterning schemes (Fig.2) are known to be feasible because all of the processes involved utilize common integration schemes, and thus there is no need to develop a special technique including the resist aspect. A common characteristic of this technique is that it often involves an etch step between two separate lithographic processes. The 2

Proceedings ArticleDOI
TL;DR: In this article, double dipole lithography is applied to the first metallization level of the CMOS process at a pitch of 100 nm using a 1.2 NA lithography system.
Abstract: The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25% smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.

10 Oct 2007
TL;DR: In this article, a novel C O M M U N IC A IO N (COMU N) pattern is created by nanoimprinting, and then used as a mask for metal film etching or metal lift-off process.
Abstract: Recent years have witnessed an expanding interest in the application of flexible polymer materials (e.g., polyimide, polyester, etc.) as the substrates for electronic and display devices. These applications include flexible organic light-emitting displays, thin film transistors, sensors, and polymer MEMS. The advantages of polymer-based materials are their mechanical flexibility, light weight, enhanced durability, and low cost compared with rigid materials (such as silicon and quartz). However, it can be difficult to integrate polymers into an integrated circuit (IC) microfabrication process due to their low thermal stability (low melting and low glass transition temperatures) and solvent susceptibility. In practice, conventional IC fabrication processes are subject to limitations, in that they are multi-step, involve high processing temperatures, caustic baths and strong solvents. In order to address the current problems of microfabrication on flexible substrate, many alternative approaches to conventional photolithography-based process have been introduced by a number of researchers. These include microcontact printing (lCP) combined with metal etching, electroless plating, electropolymerization, and direct metal layer transfer for the microscale metal patterning on flexible substrates. Stencil lithography was mainly applied for dielectric layer patterning on polymer substrates for the formation of electrical capacitors due to its limited resolution. Inkjet printing was used for a drop-on-demand patterning of conductive polymer PEDOT and gold layers for drain-source and gate electrodes. However, its best resolution is 20–50 lm limited by the nozzle diameter, the statistical variation of the droplet flight, and spreading on the substrate. Organic semiconducting materials are being widely used as semiconducting layers in flexible electronics due to their costeffectiveness, mechanical flexibility, and ease of application via specific chemical modification. However, further channel size down-scaling is essential for better performance of organic field effect transistor due to the lower carrier mobility of the organic semiconducting materials. While the abovementioned methods cannot achieve ultrafine features (a few lm’s down to ∼ 100 nm) in high aerial density and good reproducibility, nanoimprinting lithography (NIL) allows easy fabrication of precise nanoscale structures. NIL has been applied for nanopatterning in various fields such as biological nanostructures, nanophotonic devices, organic electronics, and the patterning of magnetic materials. Especially, metal nanopatterning via nanoimprinting is widely employed in nanoscale electronics and biosensing platforms. However, metal nanoimprinting has been typically an indirect process where a polymer (e.g., PMMA) pattern is first created by nanoimprinting, and then used as a mask for metal film etching or metal lift-off process. This involves multiple and expensive process steps and its chemistry is harsh for the flexible substrates. Furthermore, flexible substrates are not resistant to high temperature and pressure during the imprinting process. Recently, imprint resists based on monomer or copolymer have been developed and used for low pressure/low temperature nanoimprinting process. However, these are also indirect methods for metal nanopatterning. Very few direct metal nanoimprinting processes have been demonstrated so far due to the high melting temperature of metals. As an alternative to metal direct nanoimprinting, solid state embossing methods based upon plastic deformation of metal thin films have been introduced. These approaches involved either deformation of a metal film under very high pressure or deformation of a metal thin film/polymer multilayer under relatively lower pressure. Evidently, they are not compatible with flexible substrate since its mechanical strength is not sufficient for such processes. Additionally, these methods do not allow the fabrication of isolated, arbitrary features, and always leave unwanted residual layers. To alleviate the limitations described in the fabrication processes above, the authors have recently developed a novel C O M M U N IC A IO N

Proceedings ArticleDOI
TL;DR: In this paper, a double patterning technique was proposed to reduce the feature size of the ArF dry and wet devices by using trilayer resist including the photoresist, silicon containing bottom antireflective coatings (BARC) and planarizing organic underlay.
Abstract: In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.

Proceedings ArticleDOI
TL;DR: In this article, the authors have used a 248 nm deep-UV exposure tool and several well chosen photoresist (one is for Space application and the other is for Line application) to study the photo performance parameters in the merge of two photo exposures.
Abstract: As the semiconductor fabrication groundrule has reached the 32nm node, in general there are several possible approaches for the photolithography solution such as the double exposure with 1.35 NA immersion, the high refractive index immersion, the extremely ultra violet (EUV) lithography, nanoimprint lithography etc. Among the four, the easiest approach seems to be the double exposure method at an effective numerical aperture (NA) of 1.35. However, there are still challenges in the design and optimization of the process, such as, the use of appropriate illumination condition, the choice of a good photoresist, and the design of an optical proximity correction (OPC) strategy. Besides these considerations, there is a question as whether we really need the double etch process. To study the double exposure mechanism, we have used a 248 nm deep-UV exposure tool and several well chosen photoresist (one is for Space application and the other is for Line application) to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum groundrule we can achieve is the one for a 75 nm logic process with minimum pitch around 220 nm. One approach will be that the features with pitches wider than 440 nm are completed in a single exposure, which includes various isolated lines and spaces, line and space ends, two-dimensional structures, etc. This strategy essentially puts the single exposure pattern under the 0.18 um logic like pitches where mild conventional illumination can produce a balanced performance. Under typical illumination conditions, the photolithographic process under 0.18 um like ground rule is well understood and the optical proximity correction is not complicated. The remaining issues are in the dense pitches, where the double exposure kicks in. We have demonstrated that the double exposure with single development can achieve a process window large enough for a 75 nm logic like process and the OPC behavior such as line through pitch is manageable although OPC correction strategy may require substantial improvement to accommodate two individual exposures. In this paper, we will demonstrate the result of our study of the basic photolithographic performance indicators, such as the exposure latitude (EL), the depth of focus (DOF), the CD through pitch, the line edge roughness (LER) and the mask error factor (MEF) for the optimized process. And we will discuss the choice of photoresists for this special application. It seems that a photoresist with a balanced performance for both the line and space is necessary to realize a good double exposure process. In this paper, we will also present our simulation result of effective resist diffusion length to explore the limit of such approach.

Patent
09 Aug 2007
TL;DR: In this paper, a method for processing a photolithographic reticle includes providing a reticle having a metal photomask layer formed on an optically transparent substrate and an imprinted resist material deposited on the metal photOMask layer.
Abstract: Methods for etching a metal layer using an imprinted resist material are provided. In one embodiment, a method for processing a photolithographic reticle includes providing a reticle having a metal photomask layer formed on an optically transparent substrate and an imprinted resist material deposited on the metal photomask layer, etching recessed regions of the imprinted resist material to expose portions of the metal photomask layer in a first etching step, and etching the exposed portions of the metal photomask layer through the imprinted resist material in a second etching step, wherein at least one of the first or second etching steps utilizes a plasma formed from a processing gas comprising oxygen, halogen and chlorine containing gases. In one embodiment, the process gas is utilized in both the first and second etching steps. In another embodiment, the first and second etching steps are performed in the same processing chamber.

Proceedings ArticleDOI
Tomohiko Yamamoto1, Teruyoshi Yao1, Hiroki Futatsuya1, Tatsuo Chijimatsu1, Satoru Asai1 
TL;DR: The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well-used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET).
Abstract: The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Patent
01 May 2007
TL;DR: In this article, a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride was used to achieve an enhanced performance during the patterning of contact openings.
Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Journal ArticleDOI
TL;DR: In this article, the etch performance of amorphous Al2O3 and polycrystalline Y 2O3 films has been investigated using an inductively coupled reactive ion etch system.
Abstract: Etching of amorphous Al2O3 and polycrystalline Y2O3 films has been investigated using an inductively coupled reactive ion etch system. The etch behaviour has been studied by applying various common process gases and combinations of these gases, including CF4/O2, BCl3, BCl3/HBr, Cl2, Cl2/Ar and Ar. The observed etch rates of Al2O3 films were much higher than Y2O3 for all process gases except for Ar, indicating a much stronger chemical etching component for the Al2O3 layers. Based on analysis of the film etch rates and an investigation of the selectivity and patterning feasibility of possible mask materials, optimized optical channel-waveguide structures were fabricated in both materials. In Al2O3, channel waveguides were fabricated with BCl3/HBr plasma and using a standard resist mask, while in Y2O3, channel waveguides were fabricated with Ar and using either a resist or a sputter deposited Al2O3 mask layer. The etched structures in both materials exhibit straight sidewalls with minimal roughness and sufficient etch depths (up to 530 nm for Al2O3 and 250 nm for Y2O3) for defining waveguides with strong optical confinement. Using the developed etch processes, low additional optical propagation losses (on the order of 0.1 dB/cm) were demonstrated in single-mode ridge waveguides in both Al2O3 and Y2O3 layers at 1550 nm.

Proceedings ArticleDOI
TL;DR: In this paper, the authors focus on the finding of a suitable methodology in the printing of two-dimensional (2D) structures under the double exposure and single development scheme since it is the easiest and there is virtually no overlay concern.
Abstract: Among the three candidate approaches for 32 nm, the double exposure/patterning with 1.35 NA immersion, the high refractive index immersion, and the extremely ultra violet (EUV) lithography, the easiest approach seems to be the double exposure/patterning method at an effective numerical aperture (NA) of 1.35. However, the design and optimization of the process, such as, the choice of illu mination condition, the choice of a photoresist, and the design of an optical proximity correction (OPC) strategy for both the singly and doubly exposed patterns still need to be developed. In this paper, we will focus on the finding of a suitable methodology in the printing of two-dimensional (2D) structures under the double exposure and single development scheme since it is the easiest and there is virtually no overlay concern. We have used a 248 nm exposure tool and a well-chosen photoresist to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum ground rule we can achieve is 110 nm, similar to the one for a 75 nm logic-like process with minimum pitch of 220 nm. In the experiment, the single exposure structures are limited to pitches wider than 440 nm. In this paper, we will present a study on main process window parameters, such as, exposure latitude (EL), depth of focus (DOF), and mask error factor (MEF) for a typical 2D structure, the isolated opposing line end. We will demonstrate a near ly analytical method for the description of the line end shortening. Key words : Double Exposure, Line end shortening, LES, Effec tive resist diffusion length, partially coherent illumination

Patent
30 Oct 2007
TL;DR: In this paper, the preferred photoresists of the invention can exhibit reduced leaching of resist materials into an immersion fluid contacting the resist layer during immersion lithography processing and can be substantially non-mixable with a resin component of the resist.
Abstract: New photoresist compositions are provided that are useful for immersion lithography. Preferred photoresist compositions of the invention comprise one or more materials that can be substantially non-mixable with a resin component of the resist. Further preferred photoresist compositions of the invention comprise 1) Si substitution, 2) fluorine substitution; 3) hyperbranched polymers; and/or 4) polymeric particles. Particularly preferred photoresists of the invention can exhibit reduced leaching of resist materials into an immersion fluid contacting the resist layer during immersion lithography processing.

Patent
SiYi Li1, Helen H. Zhu1, Howard Dang1, Thomas S. Choi1, Peter Loewenhardt1 
03 May 2007
TL;DR: In this article, a low-k dielectric layer is placed over a substrate and a patterned photoresist mask is put over the layer. At least one feature is etched into the layer and a CO conditioning is performed on the feature after the feature was etched.
Abstract: A method of forming a feature in a low-k dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A CO conditioning is preformed on the at least one feature after the at least one feature is etched. The patterned photoresist mask is stripped after the CO conditioning.

Journal ArticleDOI
02 Apr 2007-Small
TL;DR: was developed, similar to opticallithography found in the semiconductor industry and elec-tron-beam lithography used in the research environment, which involves passivating the Si surface with hydrogen atoms, thus forming an atomic monolayer of hy-drogen resist.
Abstract: was developed, similar to opticallithography found in the semiconductor industry and elec-tron-beam lithography used in the research environment.The basic concept involves passivating the Si surface withhydrogen atoms, thus forming an atomic monolayer of hy-drogen resist. The extremely confined electron beam from ascanning tunneling microscopy (STM) tip is then used toremove either multiple or individual hydrogen atoms fromthis resist under certain voltage and current conditions,thereby exposing the silicon surface underneath. Thesehighly reactive dangling bonds provide adsorption sites foratomic and molecular species including oxygen,

Journal ArticleDOI
TL;DR: In this article, the authors reported the achievement of isolated 6nm wide lines in 20nm thick hydrogen silsesquioxane (HSQ) layers on silicon substrates and achieved 10nm lines and spaces in a 10nm HSQ layer.

Patent
06 Feb 2007
TL;DR: In this paper, a resist composition is provided comprising a silicone resin, a photoacid generator, a nitrogen-containing organic compound, and a solvent, which overcomes the problem of a low selective etching ratio between resist film and organic film during oxygen reactive etching.
Abstract: A resist composition is provided comprising a silicone resin, a photoacid generator, a nitrogen-containing organic compound, and a solvent The silicone resin is obtained through cohydrolytic condensation of a mixture of three silane monomers containing a fluorinated norbornane group, an organic group having a carboxyl group protected with an acid labile group, and a lactone ring-bearing organic group, respectively The resist composition has satisfactory resolution and overcomes the problem of a low selective etching ratio between resist film and organic film during oxygen reactive etching

Journal ArticleDOI
TL;DR: In this paper, a range of poly(methylmethacrylate) (PMMA) development temperatures as low as −70°C and characterized their effect on the resolution of PMMA as an electron resist.
Abstract: The authors have investigated a range of poly(methylmethacrylate) (PMMA) development temperatures as low as −70°C and characterized their effect on the resolution of PMMA as an electron resist. The results show that cooling, in addition to reducing the sensitivity of the commonly used positive-tone mode of PMMA, also increases the sensitivity of its less commonly used negative-tone mode. They have shown that the resolution-enhancing properties of cold development peak at approximately −15°C as a result of these competing sensitivity changes. At lower temperatures, the high doses required to expose the resist produce significant cross-linking of the polymer, altering its solubility properties and sharply degrading the contrast. If the correct development temperature is used, however, sub-10nm features are readily achievable in PMMA-based scanning electron-beam lithography.

Journal ArticleDOI
TL;DR: In this article, the authors show the results of sub-25 nm pitch (1Tdots∕in) patterning from both a simulation and experimental perspective, and show that the energy contrast between the exposed and unexposed areas goes down quickly as the pitch size gets smaller and smaller, making it more difficult for image formation of high-resolution dot patterning.
Abstract: Electron beam lithography presents a great opportunity for bit-patterned media (BPM) applications due to its resolution capability and placement accuracy. However, there are still many challenges associated with this application including tool availability, resist capability, process development, and associated metrology needs. This paper will briefly discuss these challenges and show the results of sub-25 nm pitch (1 Tdots∕in.2) patterning from both a simulation and experimental perspective. The simulation results indicate that the energy contrast between the exposed and unexposed areas goes down quickly as the pitch size gets smaller and smaller, making it more difficult for image formation of high-resolution dot patterning. The strategy to overcome this issue is to optimize the development process, which aims at increasing the resist contrast and enlarging the process window. By using this approach, the authors have successfully demonstrated a pitch resolution down to 18 nm for a positive-tone resist Z...

Journal ArticleDOI
TL;DR: In this article, the authors present detailed discussion of achieving high aspect ratio and high resolution x-ray zone plate through electron beam lithography, trilevel resist process and gold plating, fabrication problems, and limitations.
Abstract: Building high-performance zone plate is a critical step for achieving nanometer resolution in advanced x-ray imaging and microscopy. Zone plates with smaller outmost zone width and higher aspect ratio are increasingly in demand, simply because the resolution and efficiency of an x-ray microscope are ultimately determined by these two features. In this paper, we will present detailed discussion of achieving high aspect ratio and high resolution x-ray zone plate through electron beam lithography, trilevel resist process and gold plating, fabrication problems, and limitations. We will also present the technique to double the aspect ratio of the zone plate and measure the results of x-ray diffraction efficiency of single and aspect ratio doubled zone plates.

Journal ArticleDOI
TL;DR: In this article, the number of acid molecules generated in a model system of chemically amplified extreme ultraviolet (EUV) resists [poly(4-hydroxystyrene) film dispersed with triphenylsulfonium-triflate (TPS-tf)] was evaluated using an acid sensitive dye.
Abstract: The absorption coefficient and acid generation efficiency are elemental key factors for the design of chemically amplified resist because the acid distribution in resist films is primarily determined by these two factors. In this study, the number of acid molecules generated in a model system of chemically amplified extreme ultraviolet (EUV) resists [poly(4-hydroxystyrene) film dispersed with triphenylsulfonium-triflate (TPS-tf)] was evaluated using an acid sensitive dye. The absorption coefficient and acid generation efficiency were evaluated by changing film thickness. The acid generation efficiency was 1.7 (5 wt % TPS-tf), 2.5 (10 wt % TPS-tf), and 3.1 per photon (20 wt % TPS-tf), respectively. The absorption coefficient of the model film was 3.8±0.2 µm-1. The effect of acid generator concentration on the absorption coefficient of resist films was negligible within the concentration range of 0–20 wt %.