Topic
Resist
About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.
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27 Mar 1998TL;DR: In this paper, a resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist consisting of a crosslinkage in the presence of an acid, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern.
Abstract: A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.
70 citations
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25 Jan 2016TL;DR: In this paper, a multilayered resist is used to make an interconnect trench in an interlayer dielectric, a mixed gas including, as components thereof, at least CF 4 gas, C 3 H 2 F 4 gas and O 2 gas are used to perform dry etching.
Abstract: A semiconductor device is produced while keeping a short circuit margin between its interconnects. A method therefor includes a step in which when a multilayered resist is used to make an interconnect trench in an interlayer dielectric, a mixed gas including, as components thereof, at least CF 4 gas, C 3 H 2 F 4 gas and O 2 gas is used to perform dry etching in order to form the multilayered resist.
70 citations
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IBM1
TL;DR: The demonstrated process capabilities in terms of feature density and line-edge roughness are in accordance with today's requirements for maskless lithography, for example for the fabrication of extreme ultraviolet (EUV) masks.
Abstract: Thermal scanning probe lithography is used for creating lithographic patterns with 27.5 nm half-pitch line density in a 50 nm thick high carbon content organic resist on a Si substrate. The as-written patterns in the poly phthaladehyde thermal resist layer have a depth of 8 nm, and they are transformed into high-aspect ratio binary patterns in the high carbon content resist using a SiO2 hard-mask layer with a thickness of merely 4 nm and a sequence of selective reactive ion etching steps. Using this process, a line-edge roughness after transfer of 2.7 nm (3σ) has been achieved. The patterns have also been transferred into 50 nm deep structures in the Si substrate with excellent conformal accuracy. The demonstrated process capabilities in terms of feature density and line-edge roughness are in accordance with today’s requirements for maskless lithography, for example for the fabrication of extreme ultraviolet (EUV) masks.
70 citations
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06 Jun 2001TL;DR: In this article, the authors modeled resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity.
Abstract: In a trench-first-via-last (TFVL) dual-inlaid metal process, the thickness of resist coated in the via definition step after trench formation varies according to underlying trench topography Variation in resist thickness reduces via size uniformity and thus process window Based on the modeling of resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity Experimental results show significantly enlarged process window after proximity dummy features are inserted
70 citations
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30 Jun 1982TL;DR: In this article, a hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist.
Abstract: A hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the < 3.0 micron geometries and optical exposure of the larger sized patterns, both sets of images are developed in a single development. Using this process, working CMOS devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 micron. The effect of E-beam dosage upon the submicron gate critical dimensions has been determined as well as other processing characteristics.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
70 citations