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Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.


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Journal ArticleDOI
TL;DR: In this article, a fabrication method for freestanding complex 3D carbon microstructures utilizing a lithogaphy step and a heating step was presented, which can be used for low cost resonating microsensors and microfluidics.
Abstract: We present a fabrication method for freestanding complex 3D carbon microstructures utilizing a lithogaphy step and a heating step We developed two fabrication methods for multi-level 3D SU-8 microstructures, which were used as polymer precursors in a carbonization process In one method, multiple SU-8 layers were successively coated and cross-linked In the other method, aligned partial exposures were used to control the thickness of the freestanding SU-8 layer Freestyle, freestanding carbon microstructures were fabricated by heating 3D SU-8 microstructures below 1000 °C in a nitrogen atmosphere Characterization of the pyrolysis process, through measurements such as dimensional changes, roughness, hardness, elastic modulus and resistivity, was performed for positive resists AZ5214 and AZ9260 as well as SU-8 3D carbon microstructures fabricated using our methods can be utilized for various applications such as low cost resonating microsensors and microfluidics

59 citations

Journal ArticleDOI
TL;DR: Good accordance has been obtained between the theoretical approach and experimental results and the impact of the pattern symmetry breakdown on mould deformation is clearly shown in this paper in the printed areas as well as in the unprinted areas.
Abstract: Sub-100 nm resolution on a 200 mm silicon stamp has been hot embossed into commercial Sumitomo NEB 22 resist. A single pattern, exposed with electron beam lithography, has been considered to define the stamp and thus make it possible to point out the impact of stamp design on the printing. These results may be considered as a first attempt to define rules to solve the proximity printing effects (PPEs). Moreover, a large range of initial resist thickness, from 56 to 506 nm, has been spin coated to assess the effect of polymer flow properties for the stamp cavity filling and the printed defects. A detailed analysis of the printed resist in dense hole patterns showed that the application volume conservation is enough to calculate the residual layer thickness as the height of the printed resist feature. Good accordance has been obtained between the theoretical approach and experimental results. Moreover, the impact of the pattern symmetry breakdown on mould deformation is clearly shown in this paper in the printed areas as well as in the unprinted areas.

59 citations

Patent
29 Mar 2007
TL;DR: In this paper, a method of manufacturing a semiconductor wafer with a main surface including a device chip, a peripheral area encompassing the device chip area, and a blank area situated between the device and the peripheral area is described.
Abstract: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.

59 citations

Patent
Tokuroh Ozawa1
01 Jul 1998
TL;DR: In this paper, the authors proposed a display device in which parasitic capacitance associated with data lines and driving circuits is prevented using a bank layer whose primary purpose is to define areas on a substrate in which an organic semiconductor film is formed.
Abstract: The invention provides a display device in which parasitic capacitance associated with data lines and driving circuits is prevented using a bank layer whose primary purpose is to define areas on a substrate in which an organic semiconductor film is formed. When the organic semiconductor film for forming a luminescent element such as an electroluminescent element or an LED is formed is formed in pixel regions ( 7 ), the organic semiconductor film is formed in the areas surrounded by the bank layer (bank) formed of a black resist. The bank layer (bank) is also formed between an opposite electrode (op) and data lines (sig) for supplying an image signal to first TFTs ( 20 ) and holding capacitors (cap) in the pixel regions ( 7 ) thereby preventing parasitic capacitance associated with the data lines (sig).

59 citations

Patent
10 Jun 2004
TL;DR: In this article, the authors proposed a method to provide a semiconductor device which can increase a reliability by preventing short-circuiting of rewiring lines caused by a remaining base metallic layer.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can increase a reliability by preventing short-circuiting of rewiring lines caused by a remaining base metallic layer therebetween, and also a method of manufacturing the semiconductor device SOLUTION: The semiconductor device manufacturing method comprises steps of preparing a wafer 1 having a semiconductor substrate 3, and also having an electrode pad 5, an insulating film 7, a through hole 8 and a base metallic layer 9 provided on or in the semiconductor substrate 3; forming a first resist mask on the base metallic layer; forming a rewiring line 10 connected to the electrode pad and extended into a post electrode 11 formation region; exposing a part of the rewiring line other than the electrode formation region by removing the first resist mask and forming a second resist mask positioned away from the side face of the rewiring line; forming rewiring line protection metallic films 18 on the upper and side faces of the rewiring line; exposing the electrode formation region on the rewiring line by removing the second resist mask and applying a dry film onto the wafer; forming the post electrode; removing the dry film; and removing the rewiring line protection metallic films COPYRIGHT: (C)2008,JPO&INPIT

59 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023275
2022625
2021225
2020398
2019489
2018501