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Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.


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Patent
15 Jul 2003
TL;DR: In this article, a method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout on the substrate.
Abstract: A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.

207 citations

Journal ArticleDOI
TL;DR: In this article, a reactive ion etching process using SF6 has been developed to transfer the patterns to a depth of more than 100 nm into silicon, showing that a high contrast image is present within the resist layer, and that the exposure is dominated by one polarization for the grating structures studied.
Abstract: Patterning at resolution below the diffraction limit for projection optical lithography has been demonstrated using evanescent near-field optical lithography with broadband illumination (365–600 nm). Linewidths of 50 nm and gratings with 140 nm period have been achieved. Ultrathin photoresist layers in conjunction with conformable photomasks are employed and a reactive ion etching process using SF6 has been developed to transfer the patterns to a depth of more than 100 nm into silicon. Full electromagnetic field simulations of the exposure process show that a high contrast image is present within the resist layer, and that the exposure is dominated by one polarization for the grating structures studied.

204 citations

Journal ArticleDOI
TL;DR: In this article, a method for depositing patterned dielectric layers with submicron features using atomic layer deposition is described, which is superior to sputtered or evaporated films in continuity, smoothness, conformality, and minimum feature size.
Abstract: We report a method for depositing patterned dielectric layers with submicron features using atomic layer deposition. The patterned films are superior to sputtered or evaporated films in continuity, smoothness, conformality, and minimum feature size. Films were deposited at 100–150 °C using several different precursors and patterned using either electron-beam or photoresist. The low deposition temperature permits uniform film growth without significant outgassing or hardbaking of resist layers. A lift-off technique presented here gives sharp step edges with edge roughness as low as ∼10 nm. We also measure dielectric constants (κ) and breakdown fields for the high-κ materials aluminum oxide (κ∼8–9), hafnium oxide (κ∼16–19), and zirconium oxide (κ∼20–29), grown under similar low temperature conditions.

203 citations

Patent
Nakai Satoshi1
08 Feb 2007
TL;DR: In this article, a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate, wet-etching the first gate-insulating film of the second active region through a first resist opening portion of a first-resistance pattern, forming a second gate-inhibiting film in the second-active region, forming on the silicon substrate a second-residual pattern having a second resist portion larger than the first-Residual opening portion, and forming a third-gate insulating film
Abstract: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region

202 citations

Journal ArticleDOI
TL;DR: In this paper, a 1 in. diameter curved surface with a 46 mm radius of curvature was demonstrated with step and flash imprint lithography (SFIL) using templates patterned by ion beam proximity printing (IBP).
Abstract: Submicron patterning of 1 in. diameter curved surfaces with a 46 mm radius of curvature has been demonstrated with step and flash imprint lithography (SFIL) using templates patterned by ion beam proximity printing (IBP). Concave and convex spherical quartz templates were coated with 700-nm-thick poly(methylmethacrylate) (PMMA) and patterned by step-and-repeat IBP. The developed resist features were etched into the quartz template and the remaining PMMA stripped. During SFIL, a low viscosity, photopolymerizable formulation containing organosilicon precursors was introduced into the gap between the etched template and a substrate coated with an organic transfer layer and exposed to ultraviolet illumination. The smallest features on the templates were faithfully replicated in the silylated layer.

202 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023275
2022625
2021225
2020398
2019489
2018501