Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.

Double patterning with multilayer hard mask shrinkage for sub-0.25 k1 lithography

Abstract: In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.

Double patterning process

Abstract: Double patterns are formed by coating a first chemically amplified positive resist composition comprising an acid labile group-bearing resin and a photoacid generator and prebaking to form a resist film on a processable substrate, exposing the resist film to high-energy radiation, PEB, and developing with an alkaline developer to form a first positive resist pattern, treating the first resist pattern to be alkali soluble and solvent resistant, coating a second resist composition and prebaking to form a reversal film, and exposing the reversal film to high-energy radiation, PEB, and developing with an alkaline developer to form a second positive resist pattern. The last development step includes dissolving away the reversed first resist pattern and achieving reversal transfer.

A study of double exposure process design with balanced performance parameters for line/space applications

Abstract: As the semiconductor fabrication groundrule has reached the 32nm node, in general there are several possible approaches for the photolithography solution such as the double exposure with 1.35 NA immersion, the high refractive index immersion, the extremely ultra violet (EUV) lithography, nanoimprint lithography etc. Among the four, the easiest approach seems to be the double exposure method at an effective numerical aperture (NA) of 1.35. However, there are still challenges in the design and optimization of the process, such as, the use of appropriate illumination condition, the choice of a good photoresist, and the design of an optical proximity correction (OPC) strategy. Besides these considerations, there is a question as whether we really need the double etch process. To study the double exposure mechanism, we have used a 248 nm deep-UV exposure tool and several well chosen photoresist (one is for Space application and the other is for Line application) to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum groundrule we can achieve is the one for a 75 nm logic process with minimum pitch around 220 nm. One approach will be that the features with pitches wider than 440 nm are completed in a single exposure, which includes various isolated lines and spaces, line and space ends, two-dimensional structures, etc. This strategy essentially puts the single exposure pattern under the 0.18 um logic like pitches where mild conventional illumination can produce a balanced performance. Under typical illumination conditions, the photolithographic process under 0.18 um like ground rule is well understood and the optical proximity correction is not complicated. The remaining issues are in the dense pitches, where the double exposure kicks in. We have demonstrated that the double exposure with single development can achieve a process window large enough for a 75 nm logic like process and the OPC behavior such as line through pitch is manageable although OPC correction strategy may require substantial improvement to accommodate two individual exposures. In this paper, we will demonstrate the result of our study of the basic photolithographic performance indicators, such as the exposure latitude (EL), the depth of focus (DOF), the CD through pitch, the line edge roughness (LER) and the mask error factor (MEF) for the optimized process. And we will discuss the choice of photoresists for this special application. It seems that a photoresist with a balanced performance for both the line and space is necessary to realize a good double exposure process. In this paper, we will also present our simulation result of effective resist diffusion length to explore the limit of such approach.

Self-aligned pattern over a reflective layer

Abstract: An opening in an insulator on a substrate is self-aligned to a reflective region on the substrate. The opening is formed by shining blanket radiation on photoresist on the insulator and developing to open the resist and insulator. The resist region that is above the reflective region absorbs both incident and reflected radiation, a larger total dose of radiation than is absorbed by resist above non-reflective regions. The incident dose is adjusted to provide a below threshold dose everywhere except to those regions of resist that are above highly reflective regions.

Etching of nano-imprint templates using an etch reactor

Abstract: Methods for etching a metal layer using an imprinted resist material are provided. In one embodiment, a method for processing a photolithographic reticle includes providing a reticle having a metal photomask layer formed on an optically transparent substrate and an imprinted resist material deposited on the metal photomask layer, etching recessed regions of the imprinted resist material to expose portions of the metal photomask layer in a first etching step, and etching the exposed portions of the metal photomask layer through the imprinted resist material in a second etching step, wherein at least one of the first or second etching steps utilizes a plasma formed from a processing gas comprising oxygen, halogen and chlorine containing gases. In one embodiment, the process gas is utilized in both the first and second etching steps. In another embodiment, the first and second etching steps are performed in the same processing chamber.