Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.

Dual damascene fabrication with low k materials

Abstract: The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited Then, via lithography and via resist pattering are performed Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure

Statistical Yield Modeling for Sub-wavelength Lithography

Abstract: Photolithography is at the heart of semiconductor manufacturing process. To support continued scaling of transistors, lithographic resolution must continue to improve. At today's volume manufacturing process, a light source of 193 nm wavelength is used to print devices with 45 nm feature size. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used. While RET techniques allow printing of sub-wavelength features, the feature length itself becomes highly sensitive to process parameters, which in turn detracts from yield due to small perturbations in manufacturing parameters. Yield loss is a function of random variables such as depth-of-focus, exposure dose, lens aberration and resist thickness. The loss-of-yield is also a function of systematic components such as specific layout structure and out-of-band radiation from optical source. In this paper, we present a yield modeling technique for a given layout, based on a statistical model for process variability. The key issues addressed in this paper are (i) layout error modeling, (ii) avoidance of mask simulation for chip layouts, (iii) avoidance of full Monte-Carlo simulation for variational lithography modeling, (iv) building a methodology for yield estimation based on existing commercial tools. Results based on our approach show that yield sensitivity increases at smaller feature sizes.

New double exposure technique without alternating phase-shift mask

Abstract: The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Lithography with a mask of block copolymer microstructures

Abstract: Dense, periodic arrays of holes and troughs have been fabricated in silicon, silicon nitride, and germanium. The holes are approximately 20 nanometers (nm) wide, 20 nm deep, spaced 40 nm apart, and uniformly patterned with 3×1012 holes on a three inch wafer. To access this length scale, self-assembling resists were synthesized to produce either a layer of hexagonally ordered polyisoprene (PI) spheres or parallel cylinders of polybutadiene (PB) in a polystyrene (PS) matrix. The PI spheres or PB cylinders were then degraded and removed with ozone to produce a PS mask for pattern transfer by fluorine-based reactive ion etching. A PS mask of spherical voids was used to fabricate a lattice of holes and a mask of cylindrical voids was used to produce parallel troughs. This technique accesses a length scale difficult to produce by conventional lithography and opens a route for the patterning of surfaces via self-assembly.