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Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.


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Patent
27 Oct 1995
TL;DR: In this article, columnar electrodes are formed on the metal layer 14 in the peripheral part of the silicon substrate 21 in a wafer state, a plating resist pattern 34 is formed, electroplating is performed by using the metal layers 14 or the like as a plated current path of one side, and columnar electrode are formed in the semiconductor device.
Abstract: PROBLEM TO BE SOLVED: To enable electroplating with one plating equipment, irrespective of kinds of silicon substrates in the state of a wafer, and make the height of columnar electrodes more uniform, in a semiconductor device having the columnar electrodes formed by electroplating. SOLUTION: A tray 11 for plating is used, in which a recessed part for silicon substrate arrangement is formed in the almost central part of the upper surface of a rectangular insulating substrate 12, and a metal layer 14 is formed in a region except the recessed part for silicon substrate arrangement and specified three edge parts, on the upper surface of the insulating substrate 12. A silicon substrate 21 in a wafer state is arranged in the recessed part for silicon substrate arrangement, a plating resist pattern 34 is formed, electroplating is performed by using the metal layer 14 or the like as a plating current path of one side, and columnar electrodes are formed on the silicon substrate 21. In this case, dummy columnar electrodes are formed on the metal layer 14 in the peripheral part of the silicon substrate 21.

129 citations

Proceedings ArticleDOI
07 Jun 1996
TL;DR: In this paper, the effects of resist processing were incorporated into simulated images, and a Second Order Model based on a segmented development path was also presented, allowing the prediction of resist linewidths based on calculated image profiles.
Abstract: Process windows are frequently generated from simulated aerial image profiles by use of a threshold model for the resist process, an assumption which is not accurate for many processes. In this paper, we present new computationally efficient methods for incorporating the effects of resist processing into simulated images. The First Order Model of development leads to the simple result that the resist linewidth W is smaller than the threshold linewidth Wthresh by an amount (Delta) W approximately equals 2 [ln(D(gamma) s)-1]/((gamma) s), where D is the resist thickness, (gamma) is the resist process non-linearity and s is the log-slope of the image. A Second Order Model based on a segmented development path is also presented. These models allow the prediction of resist linewidths based on calculated image profiles for any wet developed process: optical, X-ray or e-beam lithography, both positive and negative resists. The predictions of these models show good agreement with full PROLITH/2 resist profile simulations. We have also incorporated a Fickian diffusion of the intensity profile into our model, to account for acid diffusion, stepper vibration, lens aberrations, and other effects which reduce process resolution. Experimental process windows are well matched by such models, and are significantly different than threshold model predictions.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

128 citations

Journal ArticleDOI
TL;DR: A method for reproducing diffractive optical elements in quantity is presented and involves generating a gray-scale mask employed in an optical aligner to expose an analog photoresist on any environmentally durable substrate.
Abstract: We present a method for reproducing diffractive optical elements in quantity. The method is compatible with VLSI microfabrication techniques and involves generating a gray-scale mask. The gray-scale mask is employed in an optical aligner to expose an analog photoresist on any environmentally durable substrate, e.g., glass, quartz, semiconductor, or metal, one exposure for each diffractive optical element. After copies of the mask on the photoresist are developed, many substrates can be processed in parallel in a chemically assisted ion-beam etcher to transfer the microstructures on the analog resists simultaneously onto the surfaces of the substrates.

128 citations

Journal ArticleDOI
TL;DR: The electron beam exposure system (EBES) as discussed by the authors combines continuous translation of the mask or wafer substrate with periodic deflection of the electron beam in a raster-scan mode of exposure.
Abstract: An electron beam exposure system (EBES) has proven to be practical and economic for generating high-quality fine-featured integrated circuit masks. It is also capable of exposing patterns directly on resist-coated silicon wafers and, when so used, is an effective tool with which to develop new semiconductor devices. EBES combines continuous translation of the mask or wafer substrate with periodic deflection of the electron beam in a raster-scan mode of exposure. Substrate position is monitored by means of laser interferometers. The strategy permits both the electronic and mechanical subsystems to work well within their limits of capability and contributes to system reliability. It also permits the system to be stepped up to higher resolution and faster exposure as brighter electron sources, more sensitive resist, and faster data processing techniques are developed.

128 citations

Patent
13 Sep 2001
TL;DR: In this article, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate, and an optional final step adds additional features as well as the interconnect features thus forming a circuit pattern.
Abstract: A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction. The secondary exposures are substantially independent from the initial dense-feature exposure in that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions, thus minimizing corner rounding, line end shortening and other related spatial frequency effects and unwanted exposure memory effects.

128 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023275
2022625
2021225
2020398
2019489
2018501