Resist

About: Resist is a research topic. Over the lifetime, 40991 publications have been published within this topic receiving 371548 citations.

Semiconductor wafer dividing method

Abstract: A semiconductor wafer dividing method for dividing a semiconductor wafer, on whose face side many rectangular areas are demarcated by streets arranged in a lattice fashion, along the streets to convert each of the many rectangular areas into a semiconductor chip. In this method, a resist is formed on the face side of the semiconductor wafer. Then, the resist is physically removed in areas extending along the streets. Then, an etching process is applied to the semiconductor wafer to etch the semiconductor wafer along the streets.

Manufacturing method of semiconductor device

Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.

Self-opening vent hole in an overmolded semiconductor device

Abstract: A self-opening vent hole semiconductor device (10) can be manufactured to reduce the risk of popcorning during solder reflow The device contains a semiconductor die (22) mounted on a die mounting area (15) of a substrate (12) A venting hole (16) is approximately centrally located in the die mounting area A venting hole sealing cap (20) covers and seals the venting hole A layer of patterned solder resist (18) adheres to a lower surface of the substrate The venting hole sealing cap can be made from the layer of solder resist, and can be configured to be either physically isolated from the solder resist layer or physically partially connected to the solder resist layer The venting hole sealing cap is designed to be a weakest interface within the device so that it self-opens upon an internal pressure less than a destructive pressure to the device Solder balls (30) provide external electrical connections for the device

Fabrication of 3D nanoimprint stamps with continuous reliefs using dose-modulated electron beam lithography and thermal reflow

Abstract: 3D electron beam lithography and thermal reflow were combined to fabricate structures with multilevel and continuous profiles. New shapes, smooth surfaces and sharp corners were achieved. By using exposure with variable doses, up to 20 steps were fabricated in a 500 nm thick resist with a lateral resolution of 200 nm. Steps were reflowed into continuous slopes by thermal post-processing, and were transferred into silicon substrates by proportional plasma etching. The method can be used for the fabrication of 3D nanoimprint stamps with both sharp features and continuous profiles.

Middle layer composition for trilayer patterning stack

Abstract: Methods and materials for making a semiconductor device are described. The method includes forming a middle layer (ML) of a patterning stack (e.g., a tri-layer patterning stack such as a tri-layer resist) and forming a photoresist layer directly on the middle layer. The middle layer includes an additive component having a photo base generator (PBG). The substrate including the photoresist layer and the middle layer is then exposed to a radiation. A covalent bond between the ML and the photoresist layer may be formed.