Resistive random-access memory

About: Resistive random-access memory is a research topic. Over the lifetime, 6883 publications have been published within this topic receiving 143134 citations. The topic is also known as: RRAM & ReRAM.

Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures

Abstract: The impact of device and circuit-level effects in mixed-signal Resistive Random Access Memory (RRAM) accelerators typically manifest as performance degradation of Deep Learning (DL) algorithms, but the degree of impact varies based on algorithmic features. These include network architecture, capacity, weight distribution, and the type of inter-layer connections. Techniques are continuously emerging to efficiently train sparse neural networks, which may have activation sparsity, quantization, and memristive noise. In this paper, we present an extended Design Space Exploration (DSE) methodology to quantify the benefits and limitations of dense and sparse mapping schemes for a variety of network architectures. While sparsity of connectivity promotes less power consumption and is often optimized for extracting localized features, its performance on tiled RRAM arrays may be more susceptible to noise due to under-parameterization, when compared to dense mapping schemes. Moreover, we present a case study quantifying and formalizing the trade-offs of typical non-idealities introduced into 1-Transistor-1-Resistor (1T1R) tiled memristive architectures and the size of modular crossbar tiles using the CIFAR-10 dataset.

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiO<SUB>x</SUB> Buffer Layer for RRAM Passive Crossbar Array

Abstract: As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al₂O₃/TiOSUBx/SUB/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOSUBx/SUB encompassing metallic and semiconducting properties; and three devices with different TiOSUBx/SUB were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiOSUB1.74/SUB sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 2SUP7/SUP × 2SUP7/SUP array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

Analog NVM Synapse for Hardware-Aware Neural Network Training Optimization on 65nm CMOS TaOₓ ReRAM Devices

Abstract: Deep Learning (DL) applications using Analog Neuromorphic Network (ANN) applications require linear, symmetric, and multilevel conductance modulation for high accuracy results. These requirements have led to the heavy use of GPUs for ANN applications. However, due to large power requirements for ANN, Non-Volatile Memory (NVM) devices such as Resistive Random Access Memory (ReRAM) are being investigated due to their lower power and lower area usage compared to conventional CMOS. In this work, using our 65nm CMOS integrated TaO x ReRAM devices, we explore the effects of parameter adjustment for voltage and current controlled device operation in constant pulse programming cases and operational differences with incremental pulse programming. We present a simple statistical model for symmetry and linearity and explore the effect of linearity mismatch on cycle-to-cycle variability, switching pulse variation, and finally the effect on Neural Network (NN) learning using a “Cross-Sim” simulator trained on the MNIST dataset for handwritten digit recognition.

Apparatus and method of in-memory computation using non-volatile arrays

Abstract: Described is an apparatus which comprises: a first word-line; a first bit-line; a second bit-line; a first resistive memory cell having a first terminal coupled to the first bit-line and a second terminal coupled to the first word-line; a second resistive memory cell having a first terminal coupled to the second bit-line and a second terminal coupled to the first word-line; and a first integrator coupled to the first word-line.

Operation method of resistive memory device

Abstract: A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.