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Rise time

About: Rise time is a research topic. Over the lifetime, 4748 publications have been published within this topic receiving 47512 citations.


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Patent
David B. Bell1
18 Dec 2001
TL;DR: In this article, circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line Signal line voltage is monitored to determine if the signal line is being pulled or not, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided.
Abstract: Circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line Signal line voltage is monitored to determine if the signal line is being pulled LOW If the signal line is not being pulled LOW, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided The additional current may be provided gradually in relation to the signal line voltage, or may be provided in full whenever voltage exceeds the threshold Circuitry may also be provided to monitor voltage slew rate on the signal line, and to enable the additional pullup current only when the slew rate exceeds a positive threshold level

24 citations

Journal ArticleDOI
01 Aug 1996
TL;DR: It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance.
Abstract: Design trade-off relations for the last stage of a complementary metal-oxide-semiconductor (CMOS) off-chip driver that meets a prespecified normalized maximum simultaneous switching ground noise and a prespecified normalized time when the switched N-channel metal-oxide-semiconductor transistor (NMOST) leaves the saturation region are provided in this paper. To maintain system performance with control of 90-10% fall time and/or 10-90% rise time, the proposed trade-off relations are then modified numerically for design with prespecified fall/rise time. The proposed trade-offs relate the normalized simultaneous switching noise and the normalized switching time to driver size, load capacitance, ground/power path inductance, number of switching drivers, and input signal rise time. It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance. Such a feature will be demonstrated by SPICE simulations of circuits based upon the proposed design relations and MOS1 model, which agrees well with the design goals.

24 citations

Journal ArticleDOI
TL;DR: In this paper, the logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators.
Abstract: In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits.

24 citations

Proceedings ArticleDOI
N. Foulon1, J.-P. Lucas, G. Barre, R. Mailfert, J. Enon 
22 Sep 1997
TL;DR: In this article, a fast voltage surge generator and laboratory cells have been built, to study partial discharge development and material degradation according to voltage magnitude, polarity, rise time and surge repetition rate.
Abstract: Electrical rotating machines are subjected to nonsinusoidal wave shapes when supplied from high frequency inverters. PWM (pulse width modulated) voltage sources with steep wave fronts can be destructive to the insulation and criteria normally used under sinusoidal conditions cannot necessarily be transposed to this new case. In order to determine the influence of this electrical stress, laboratory experiments were carried out to determine whether such repetitive voltage surges can precipitate premature failure of high voltage motor windings. A fast voltage surge generator and laboratory cells have been built, to study partial discharge development and material degradation according to voltage magnitude, polarity, rise time and surge repetition rate. Partial discharges (PD) are strongly dependent on the voltage waveform, related to the statistical time lag which is necessary before PD inception. Physical and chemical analysis and surface potential decay measurements show that the ageing process is related to the voltage waveform (frequency, shape factor, etc.). It is suggested that under PWM operation, insulation ageing mechanisms are predominantly controlled through an electrostatic phenomenon, different from the 50/60 Hz sinusoidal case.

24 citations

Journal ArticleDOI
TL;DR: In this article, a time domain study of the frequency transition of spin-torque oscillator (STO) under the magnetic-field pulse in nanosecond range is presented.
Abstract: We report a time domain study of the frequency transition of spin-torque oscillator (STO) under the magnetic-field pulse in nanosecond range. We fabricated the pillar-structured STO devices consisting of MgO-based tunnel junctions with CoFeB free layers. Single-shot waveforms of the STO were obtained using a real-time oscilloscope (40 GS/sec). First, we measured current dependence of the waveform to investigate the time-domain stability of the oscillation. With the increase in the dc current applied to the STO, the oscillation state changed continuously in the following order: thermal fluctuation, intermittent unsteady oscillation, steady oscillation, and chaotic oscillation. Next, we measured the response of the STO to the magnetic-field pulse with a rise time of 0.5 ns, a duration time of 10 ns, and an amplitude of 60 Oe. In this measurement, the oscillation state was kept in the above-mentioned steady state with the frequency ∼3.5 GHz and the spectral linewidth ∼50 MHz. In the presence of the magnetic-...

24 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202264
2021111
2020146
2019157
2018147