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Rise time

About: Rise time is a research topic. Over the lifetime, 4748 publications have been published within this topic receiving 47512 citations.


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Journal ArticleDOI
TL;DR: A sampling oscilloscope is described with a 10 to 90% rise time of 5.6×10−10 sec, and pulses of constant or random repetition rate are displayed with equal facility.
Abstract: A sampling oscilloscope is described with a 10 to 90% rise time of 5.6×10−10 sec. Maximum useful sweep speed is about 10−10 sec/in.; maximum useful sensitivity about 15 mv/in. These are limited solely by the peak time jitter of 2×10−11 sec, and apparent input peak noise of about 300 μv. Unlike prior sampling devices, pulses of constant or random repetition rate are displayed with equal facility. The usual time jitter associated with the display of random pulse heights is eliminated by selecting for display only those pulses that fall within a kicksorter channel. The average wave form of pulses with moderately irregular shapes is particularly easy to measure.

65 citations

Journal ArticleDOI
TL;DR: In this article, the impact of discrete dopants on device characteristics is investigated in 16-nm-gate CMOS circuits, and the authors provide an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field effect transistor circuits.
Abstract: The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.

65 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed a pulsed-reset operation of the drift detector in charge sensitive amplifier (CSA) configuration, where the signal charge is removed by applying short reset pulses to a reset structure integrated on the detector anode.
Abstract: Silicon Drift Detectors with integrated FET transistor fabricated at Max-Planck-Institute in Munich in cooperation with PNSensor GmbH are widely used as X-ray sensors in many industrial and scientific applications. In the classical readout scheme, the integrated transistor on the SDD is operated in the source–follower configuration. The signal charge is removed continuously by the detector self-rest mechanism. The method gives very good results at counting rates up to 10 kcps. For higher count rates, the FWHM increases with the growing reset current and a slight shift of the energy peak is observed. The relative large signal rise time can be also a limitation for operation at very high count rates. Alternatively, the SDD can be operated in a Charge Sensitive Amplifier (CSA) configuration. The detector signal charge is integrated on a feedback capacitor across an inverting amplifier with the integrated FET as the input transistor. The signal rise time does not depend on the integrated transistor and can be made very short (e.g. 50 ns). In applications requiring very high counting rates and constant energy resolution, pulsed-reset operation of the SDD is desirable. The signal charge is removed by applying short reset pulses to a reset structure integrated on the detector anode. The combination of the CSA readout scheme and the pulsed-reset method allows the operation at the best energy resolution independent on the count rate.

65 citations

Journal ArticleDOI
TL;DR: In this paper, the high frequency response characteristics of differentiating and self-integrating Rogowski coils have been calculated for arbitrary values of the coil terminating resistance assuming Ampere's law to be valid.
Abstract: The high frequency response characteristics of differentiating and self-integrating Rogowski coils have been calculated for arbitrary values of the coil terminating resistance assuming Ampere's law to be valid. Effects due to a reactive terminating impedance are also discussed. When the displacement current is taken into account in the measurement of the current of a charged particle beam, it is found that an effective rise time is introduced into the self-integrating coil response on the order of a/??, where a is the major radius of the coil, ? is the velocity of the beam, and ? = (1 -?2/c2)-1/2.

65 citations

Patent
17 Jun 2002
TL;DR: In this article, an RNG circuit is connected to the parallel port of a computer, which includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range.
Abstract: An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

63 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202264
2021111
2020146
2019157
2018147