Showing papers on "RLC circuit published in 1999"

Semi-passive damping using continuous switching of a piezoelectric device

Abstract: Passive damping using a piezoelectric device is a well-known technique. Both resistor and inductor loads connected to the piezoceramic are commonly used to attenuate a given resonance mode on a structure equipped with piezo dampers. The main drawback of this technique is its narrow band behavior and especially in the case of an inductor tuned passive piezo damper. The proposed technique is inherently wide band and does not rely on any tuned electric load. The piezoelectric device is simply continuously switched from open-circuit to short-circuit synchronously to the mechanical strain. It is called semi-passive because of the need of a sensor giving the strain of the piezo device. There is no need for external power supply unless for the low-level circuitry of the switch device. The damping efficiency appears to be twice what is obtained with pure resistive damping and is equivalent to what is achievable with a tuned inductor damper. It can work at any frequency without the need for large inductor especially for low frequency applications. A qualitative model gives an understanding of the damping mechanism.

Figures of merit to characterize the importance of on-chip inductance

Abstract: A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-/spl mu/m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.

DC ripple current reduction on a single-phase PWM voltage source rectifier

Abstract: A novel topology of single-phase pulsewidth modulation (PWM) voltage-source rectifier capable of achieving not only a sinusoidal input current, but also a zero-ripple output current, is presented. The rectifier consists of a conventional single-phase PWM voltage-source rectifier, a pair of additional switches and an inductor. Hence, the proposed rectifier requires neither a large DC capacitor nor a passive L-C resonant circuit. The input current control is achieved by the conventional PWM current control technique. However, DC ripple current reduction control is difficult because one of the switching legs in the DC ripple current reduction circuit is shared with the PWM rectifier circuit. Two control methods, referred to here as the DC C inductor method and the AC inductor method, are proposed for DC ripple reduction, and the characteristics of these control methods are discussed. These control methods are implemented using a microprocessor, and the effectiveness of the circuit is confirmed experimentally. This rectifier has useful applications in uninterruptible power systems and DC power supplies, especially for cases in which the batteries are connected in parallel to the DC line.

PLECS-piece-wise linear electrical circuit simulation for Simulink

Abstract: In this paper a new toolbox, PLECS, for the fast simulation of power electronic circuits under Simulink is presented. This toolbox provides the means for modeling large power electronic systems containing both electrical circuits and controllers. The program is based on a state-space formulation for circuits that consist of linear elements (RLC), transformers, sources, meters and ideal switches. Diodes, thyristors, IGBTs and other nonlinear elements such as saturable inductors can be assembled by combining linear elements and switches. Thus, a piece-wise linear model is attained which leads to a stable and fast simulation. An attached benchmark simulation demonstrates the capability of PLECS.

ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization

Abstract: ENOR is an innovative way to produce provably-passive, reciprocal, and compact representations of RLC circuits. Beginning with the nodal equations, ENOR formulates recurrence relations for the moments that involve factorizing a symmetric, positive definite matrix; this contrasts with other RLC order reduction algorithms that require expensive LU factorization. It handles floating capacitors, inductor loops, and resistor links in a uniform way. It distinguishes between active and passive ports, does Gram-Schmidt orthogonalization on the fly, controls error in the time-domain. ENOR is a superbly simple, flexible, and well-conditioned algorithm for lightning reduction of mega-sized RLC trees, meshes, and coupled interconnects-all with excellent accuracy.

Rfid tag having parallel resonant circuit for magnetically decoupling tag from its environment

Abstract: An RFID tag circuit provides magnetic decoupling and amplitude modulation. The circuit is made up of a first inductor and a second inductor connected in series, a first capacitor, a second capacitor, and a switch. The circuit includes a first resonant circuit formed from a parallel connection of the series connected first and second inductors, and the first capacitor. The first resonant circuit has a primary resonant frequency. The circuit also includes a second circuit formed from a series connection of the second capacitor and the switch. The series connection of the second capacitor and the switch are connected in parallel to the second inductor. One end of the series connected second capacitor and switch is connected to the common connection between the series connected first and second inductors.

Self-sustained oscillating resonant converters operating above the resonant frequency

Abstract: This paper presents a new control technique for resonant converters. Unlike conventional variable frequency control which externally imposes the switching frequency, the proposed scheme is based on controlling the displacement angle between one of the resonant circuit variables, typically the current through the resonant inductor, and the voltage at the output of the inverter. As a result, zero-voltage switching (ZVS) can be ensured over a wide operating range. The proposed control technique cam be applied for series, parallel, and series-parallel resonant converters. As an example, the static characteristics and dynamic model of a series-parallel resonant converter with the proposed controller are derived and the system behaviour is investigated in detail. Experimental results are given to demonstrate the operation of resonant converters with the proposed controller and to validate the analysis.

High intensity discharge lamp ballast

Abstract: A low current loss ballast operates a high intensity discharge lamp with or without radioactive krypton. A by-pass capacitor in conjunction with a resonant strike circuit limits high frequency ripple applied to a lamp during continuing operation. Different resistor combinations are connected to drive dual buck converters of the ballast. One combination is used for high frequency operation for striking. Another combination is used during low frequency operation to limit current loss. In a strike mode of operation, combinations of signals at a resonant frequency for striking and subharmonic frequencies are applied to a resonant circuit. The signals at the subharmonic have less than a 50% duty cycle.

Equivalent Elmore delay for RLC trees

Abstract: Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented, These solutions have the same accuracy characteristics as the Elmore delay model for RC trees and preserves the simplicity and recursive characteristics of the Elmore delay. The solutions introduced here consider all damping conditions of an RLC circuit including the underdamped response, which is not considered by the classical Elmore delay model due to the non-monotone nature of the response. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for RLC trees can be practically used for the same purposes that the Elmore delay is used for RC trees.

Modeling of power distribution systems for high-performance microprocessors

Abstract: This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information.

Clock recovery using an injection tuned resonant circuit

Abstract: A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream. The slave oscillator in turn generates a recovered clock signal. In another application, a sub-harmonic clock signal in a 5.6 Gb/s NRZ (Non Return to Zero) 2 7 −1 pseudo-random data stream is used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is de-serialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock.

Practical considerations for passive reduction of RLC circuits

Abstract: Krylov space methods initiated a new era for RLC circuit model order reduction. Although theoretically well-founded, these algorithms can fail to produce useful results for some types of circuits. In particular, controlling accuracy and ensuring passivity are required to fully utilize these algorithms in practice. In this paper we propose a methodology for passive reduction of RLC circuits based on extensions of PRIMA, that is both broad and practical. This work is made possible by uncovering the algebraic connections between this passive model order reduction algorithm and other Krylov space methods. In addition, a convergence criteria based on an error measure for PRIMA is presented as a first step towards intelligent order selection schemes. With these extensions and error criterion, examples demonstrate that accurate approximations are possible well into the RF frequency range even with expansions about s=0.

System for item and orientation identification

Abstract: A system includes an identification circuit, a grid antenna, a receiver, and a processor. The identification circuit includes resonant circuits formed on a substrate within a perimeter. Identification may be based on a quantity or physical arrangement of detected resonant circuits within the perimeter. One resonant circuit provides a reference signal. Any resonant circuit may be tuned in accordance with the reference signal by the addition or subtraction of reactance formed on the substrate. A capacitance of a first group of capacitors located outside a turn of an inductor is roughly equal to a capacitance of a second group of capacitors located inside the turn. Any resonant circuit may also be tuned by affixing a resonance modifying element, for example a sticker, to the identification circuit. The grid antenna provides antenna field patterns, one for each cell location. The receiver communicates with the identification circuit via the grid antenna. The processor controls the receiver according to a method including: (a) detecting a first signal at a first grid location; (b) determining an offset as a difference between a frequency of the first signal and a predetermined frequency; (c) detecting a second signal at a second grid location; (d) determining an identification in accordance with the first and second locations, the second signal, the offset determined in step (b), and any offset accomplished by a sticker; and (e) determining an orientation in accordance with the first and second grid locations.

LLCC resonant inverter for piezoelectric ultrasonic motor drive

Abstract: An LLCC resonant circuit is implemented in this study to build a high-frequency two-phase voltage source inverter for the piezoelectric ultrasonic motor (USM). A single-phase equivalent model of the USM is described. The operating principle and detailed analysis of the proposed driving circuit, in which the inherent parasitic capacitances formed by the polarised piezoelectric ceramic of the USM are parts of the two LLCC resonant circuits, are introduced. Since the dynamic characteristic of the USM is greatly influenced by the variation in the Q of the RLC resonant tanks, the drive will be operated about a geometric frequency where the amplitude and phase of the two-phase output voltages of the resonant inverter would not be influenced by the variation in Q. Detailed experimental results are provided to demonstrate the effectiveness of the proposed driving circuit.

An MMIC active phase shifter using a variable resonant circuit [and MESFETs]

Abstract: This paper describes a monolithic-microwave integrated-circuit (MMIC) active phase shifter using a variable resonant circuit with a large amount of variable phase. We first propose a novel active phase-shifter configuration that uses a variable resonant circuit with second-order all-pass network characteristics. Phase can be changed with a constant amplitude by varying the capacitance or the inductance of the resonant circuit. Next, an experimental MMIC active phase shifter with input active matching is presented. A phase shift of over 100/spl deg/ and an insertion loss of 4/spl plusmn/1 dB are obtained from 2.2 to 2.8 GHz. The chip size is less than 1.0 mm/sup 2/. Finally, an experimental 360/spl deg/ MMIC active phase shifter is presented. Over the bandwidth of 40 MHz at 2.44 GHz, the insertion gain is 2.0/spl plusmn/0.7 dB and the phase error is within /spl plusmn/4/spl deg/ when measured in 30/spl deg/ steps.

Positive-negative pulse type high frequency switching power supply unit

Abstract: The invention provides a positive-negative type high frequency switching power supply unit which provides a high frequency output of an ideal sine waveform to allow reliable switching with very low switching loss without being influenced by a leakage inductance of the load side, a parasitic capacitance and a parasitic inductance produced by a wiring line or the like, and a load condition. The positive-negative type high frequency switching power supply unit includes an H-bridge switching circuit including four semiconductor switching elements connected in an H-bridge connection, a resonance circuit which resonates with a positive-negative pulse wave outputted from the H-bridge switching circuit, and a PWM control circuit for detecting a voltage and current of the resonance circuit by means of a pulse transformer and a current detector, respectively, and feeding back the voltage and current to the H-bridge switching circuit so that the four semiconductor switching elements may perform switching operations in a switching frequency higher than the resonance frequency of the resonance circuit in a fixed switching pattern of on/off states.

A history of network synthesis and filter theory for circuits composed of resistors, inductors, and capacitors

Abstract: This paper is an informal history of the birth and growth of network synthesis and filter theory, as it was developed for RLC circuits. It includes events, experiences, and anecdotes which are not all well documented but may make interesting reading. Other papers in this issue are histories of other aspects of circuit theory; for the most part descended from the RLC theory.

Broadband equivalent circuit of a dipole antenna

Abstract: A broadband equivalent circuit of a dipole antenna valid from very low frequency to its second resonance, consisting of a series resonant circuit and two parallel resonant circuits, with frequency independent lumped elements is presented. Empirical formulas for the elements in the proposed equivalent circuit are given. Feed-point impedances calculated using the present equivalent circuit are compared with those obtained from Zeland Software's IE3D simulator, version 5.

Solid state RF oscillator-detector for flow cytometer

Abstract: A junction field effect transistor (JFET) RF oscillator-detector circuit generates an RF signal for an apparatus for conducting electrical measurements of particles contained in a carrier fluid passing through an aperture in a cytometer flow cell The JFET oscillator includes a plurality of parallel-coupled JFETs having respectively different VDS vs IDS characteristics, that are biased to operate at square law detection regions of their respective VDS vs IDS characteristics One JFET operates in Class C mode, while the other operates in Class AB mode An RF resonant circuit is electrically coupled to the JFETs and to the measurement cell, and is operative to establish the frequency of an RF field applied to the measurement cell An RF load change detection circuit is coupled to the RF resonator circuit and is operative to detect an RF load change associated with a modification of the RF field as a result of a particle within the measurement cell aperture

Partial resonance PWM converter

Abstract: The present invention provide a partial resonance PWM converter capable of making the switching loss occurring at a switch approximately zero and high efficiency by controlling a switching timing. A series circuit composed of upper and lower main switches is connected in parallel with a DC power supply, and diodes are respectively connected in parallel with each of the main switches in the opposite direction of a polarity of the DC power supply. A series circuit composed of upper and lower auxiliary switches is connected in parallel with the DC power supply, and diodes are respectively connected in parallel with each of the auxiliary switches in the opposite direction of the polarity of the DC power supply. A series resonance circuit composed of a capacitor and an inductor is inserted between the juncture of the upper and lower main switches and a juncture of the upper and lower auxiliary switches. The switching timing is controlled to make the auxiliary switch turn on just before the main switch is switched, to make the main switch turn off during the diode connected in parallel with each of the main switches is in ON condition, and to make the auxiliary switch turn off during the ON condition of the diode connected in parallel with each of the auxiliary switches.

Effect of the loaded quality factor on power efficiency for CMOS class-E RF tuned power amplifiers

Abstract: An analytical expression for the harmonic distortion and power efficiency for class-E power amplifiers is derived. By considering the nonideal behavior of the switching device, we explore the dependence of power efficiency on the quality factor of the resonant circuit, as well as the current decay angle of the active device. The result is very useful since it predicts the power efficiency in terms of circuit parameters. The analytical expression is supported by good agreement with circuit simulations.

Non-contact type ic card and method for regulating antenna characteristics

Abstract: PROBLEM TO BE SOLVED: To provide a non-contact type IC card containing regulating capacitor and resistor to regulate a sharpness of a resonance circuit by regulating a resistance value in the circuit and a method for regulating its antenna characteristics. SOLUTION: This non-contact type IC card communicates with an external reader/writer in a non-contact manner. In this case, the IC card has a resonance circuit having an antenna coil 13 and a planar regulating resistor in a card base, and can assure a good communicating state by regulating a sharpness Q of the circuit by regulating a resistance value of the regulating resistor 14 in the circuit. A regulating capacitor 15 is provided, and a resonance frequency (f) can be regulated. Antenna characteristic regulation of the IC card can be conducted by regulating the sharpness Q by cutting a part of a plurality of the circuits provide by branching from the antenna coil. COPYRIGHT: (C)2001,JPO

Switching power supply

Abstract: A plurality of power supply circuits Z 1 ′ are provided according to a load capacity The power supply circuits Z 1 ′ have sides connected in parallel on the side of a direct current input Vi and have sides connected in series on the sides of alternating current outputs Ao A rectifying circuit DC 1 is connected via a resonance circuit Z 2 across a combined output of the serially connected sides of the power supply circuits Z 1 ′ on the sides of the alternating current outputs Ao Switching frequencies are simultaneously controlled by a single control signal outputted from a control circuit S 1 based on a direct current output voltage detected from the rectifying circuit DC 1 through a detection resistor R 5

Repeater insertion in tree structured inductive interconnect

Abstract: The effects of inductance on repeater insertion in RLC trees is the focus of the paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible repeater positions, permitting a repeater solution to be chosen that is close to the global minimum. The repeater insertion algorithm is used to insert repeaters within several copper based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper based interconnect trees from a 0.25 /spl mu/m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2% and 9.4%, respectively, when using five times faster devices with the same interconnect trees.

Enhanced lc filter with tunable q

Abstract: A tunable electronic filter circuit is provided including an input terminal and an output terminal connected to the input terminal with a node therebetween. An inductor, a variable capacitor, and a variable resistor are connected between the node and ground. Coupled to the variable capacitor and the variable resistor is a feedback control circuit. The feedback control circuit is operable to tune the variable capacitor in order to set a predetermined frequency, or center frequency, of the electronic filter circuit. The feedback control circuit is further operable to tune the variable resistor in order to calibrate a quality factor of the electronic filter circuit. In use when an input signal is applied to the input terminal, the electronic filter circuit passes an output signal to the output terminal. Such output signal includes components of the input signal within a predetermined frequency bandwidth set by the predetermined frequency and filters out other components of the input signal. As an option, a “slave” tunable electronic filter circuit may be providing including a variable capacitor and a variable resistor which are also controlled by the feedback circuit. This allows the “slave” filter to be tuned while being used.

Method and apparatus for the wireless capture of coordinate-shift information

Abstract: An apparatus is provided for the wireless capture of coordinate-shift information. The apparatus includes a pulse generator that generates a pulse signal and simultaneously distributes the pulse signal into a first signal along the first path and a second signal along the second path. The apparatus further includes a working area defined by a plurality of crossing X-axis signal lines and Y-axis signal lines, and at least one coil surrounding the working area for generating a magnetic field. The apparatus also includes a scanning circuit coupled to the working area, and a synchronic determination circuit coupled to the pulse generator and the scanning circuit for receiving the first and second signals, and for determining the time delay between the receipt of the first and second signals. The apparatus further includes a signal processing circuit coupled to the scanning circuit and the synchronic determination circuit. The first signal passes through the working area and the scanning circuit to the synchronic determination circuit, and contains coordinate shift information. The position indicator can include a resonance circuit that receives signals from the magnetic field, and then re-transmits resonance signals having different pulse widths to the working area.

Self-sensing magnetic levitation using a LC resonant circuit

Abstract: A self-sensing magnetic levitation system utilizing a LC resonant circuit is proposed by using the characteristic that the inductance of the magnetic system is varied with respect to the air gap displacement. An external capacitor is added into the electric system to make the levitation system statically stable, which much relieves the control effort required to stabilize the magnetic levitation system of having an intrinsic unstable nature. For the realization of the self-sensing magnetically levitated system, an amplitude modulation/demodulation method is used with a positive position feedback controller. Experimental results are presented to validate the proposed method.

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

Abstract: The dynamic and short-circuit power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving an inductance-capacitance (LC) transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed-form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. A closed form solution for the short-circuit power is also presented. These solutions agree with circuit simulations within 11% error for a wide range of transistor widths and line impedances for a 0.25-/spl mu/m CMOS technology. The ratio of the short circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects becomes more significant as compared to a resistance-capacitance (RC)-dominated interconnect line.

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

Abstract: A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the traditional quadratic dependence of the propagation delay on the length of an RC line approaches a linear dependence as inductance effects increase. The closed form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. An RC model as compared to an RLC model creates errors of up to 30% in the total propagation delay of a repeater system. Considering inductance in repeater insertion is also shown to significantly save repeater area and power consumption. The error between the RC and RLC models increases as the gate parasitic impedances decrease which is consistent with technology scaling trends. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.